Mesa (master): aco: optimize v_and(a, v_subbrev_co(0, 0, vcc)) -> v_cndmask(0, a, vcc)
GitLab Mirror
gitlab-mirror at kemper.freedesktop.org
Mon Nov 9 17:50:57 UTC 2020
Module: Mesa
Branch: master
Commit: bae5487659636fbbb79021f89ba01ba32e4a3abc
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=bae5487659636fbbb79021f89ba01ba32e4a3abc
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Tue Nov 3 18:50:32 2020 +0100
aco: optimize v_and(a, v_subbrev_co(0, 0, vcc)) -> v_cndmask(0, a, vcc)
fossils-db (Vega10):
Totals from 7786 (5.70% of 136546) affected shaders:
SGPRs: 517778 -> 518626 (+0.16%); split: -0.01%, +0.17%
VGPRs: 488252 -> 488084 (-0.03%); split: -0.04%, +0.01%
CodeSize: 42282068 -> 42250152 (-0.08%); split: -0.16%, +0.09%
MaxWaves: 35697 -> 35716 (+0.05%); split: +0.06%, -0.01%
Instrs: 8319309 -> 8304792 (-0.17%); split: -0.18%, +0.00%
Cycles: 88619440 -> 88489636 (-0.15%); split: -0.16%, +0.01%
VMEM: 2788278 -> 2780431 (-0.28%); split: +0.06%, -0.35%
SMEM: 570364 -> 569370 (-0.17%); split: +0.12%, -0.30%
VClause: 144906 -> 144908 (+0.00%); split: -0.05%, +0.05%
SClause: 302143 -> 302055 (-0.03%); split: -0.04%, +0.01%
Copies: 579124 -> 578779 (-0.06%); split: -0.14%, +0.08%
PreSGPRs: 327695 -> 328845 (+0.35%); split: -0.00%, +0.35%
PreVGPRs: 434280 -> 433954 (-0.08%)
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02 at gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7438>
---
src/amd/compiler/aco_optimizer.cpp | 46 ++++++++++++++++++++++++++++++-
src/amd/compiler/tests/test_optimizer.cpp | 42 ++++++++++++++++++++++++++++
2 files changed, 87 insertions(+), 1 deletion(-)
diff --git a/src/amd/compiler/aco_optimizer.cpp b/src/amd/compiler/aco_optimizer.cpp
index 9a8d6d9fe2f..aa9fad589b3 100644
--- a/src/amd/compiler/aco_optimizer.cpp
+++ b/src/amd/compiler/aco_optimizer.cpp
@@ -1401,6 +1401,7 @@ void label_instruction(opt_ctx &ctx, Block& block, aco_ptr<Instruction>& instr)
case aco_opcode::v_add_co_u32_e64:
case aco_opcode::s_add_i32:
case aco_opcode::s_add_u32:
+ case aco_opcode::v_subbrev_co_u32:
ctx.info[instr->definitions[0].tempId()].set_add_sub(instr.get());
break;
case aco_opcode::s_not_b32:
@@ -2267,7 +2268,7 @@ bool combine_add_sub_b2i(opt_ctx& ctx, aco_ptr<Instruction>& instr, aco_opcode n
new_instr->operands[1] = instr->operands[!i];
new_instr->operands[2] = Operand(ctx.info[instr->operands[i].tempId()].temp);
instr = std::move(new_instr);
- ctx.info[instr->definitions[0].tempId()].label = 0;
+ ctx.info[instr->definitions[0].tempId()].set_add_sub(instr.get());
return true;
}
}
@@ -2556,6 +2557,47 @@ bool apply_omod_clamp(opt_ctx &ctx, Block& block, aco_ptr<Instruction>& instr)
return true;
}
+/* v_and(a, v_subbrev_co(0, 0, vcc)) -> v_cndmask(0, a, vcc) */
+bool combine_and_subbrev(opt_ctx& ctx, aco_ptr<Instruction>& instr)
+{
+ if (instr->usesModifiers())
+ return false;
+
+ for (unsigned i = 0; i < 2; i++) {
+ Instruction *op_instr = follow_operand(ctx, instr->operands[i], true);
+ if (op_instr &&
+ op_instr->opcode == aco_opcode::v_subbrev_co_u32 &&
+ op_instr->operands[0].constantEquals(0) &&
+ op_instr->operands[1].constantEquals(0) &&
+ !op_instr->usesModifiers()) {
+
+ aco_ptr<Instruction> new_instr;
+ if (instr->operands[!i].isTemp() && instr->operands[!i].getTemp().type() == RegType::vgpr) {
+ new_instr.reset(create_instruction<VOP2_instruction>(aco_opcode::v_cndmask_b32, Format::VOP2, 3, 1));
+ } else if (ctx.program->chip_class >= GFX10 ||
+ (instr->operands[!i].isConstant() && !instr->operands[!i].isLiteral())) {
+ new_instr.reset(create_instruction<VOP3A_instruction>(aco_opcode::v_cndmask_b32, asVOP3(Format::VOP2), 3, 1));
+ } else {
+ return false;
+ }
+
+ ctx.uses[instr->operands[i].tempId()]--;
+ if (ctx.uses[instr->operands[i].tempId()])
+ ctx.uses[op_instr->operands[2].tempId()]++;
+
+ new_instr->operands[0] = Operand(0u);
+ new_instr->operands[1] = instr->operands[!i];
+ new_instr->operands[2] = Operand(op_instr->operands[2]);
+ new_instr->definitions[0] = instr->definitions[0];
+ instr = std::move(new_instr);
+ ctx.info[instr->definitions[0].tempId()].label = 0;
+ return true;
+ }
+ }
+
+ return false;
+}
+
// TODO: we could possibly move the whole label_instruction pass to combine_instruction:
// this would mean that we'd have to fix the instruction uses while value propagation
@@ -2814,6 +2856,8 @@ void combine_instruction(opt_ctx &ctx, Block& block, aco_ptr<Instruction>& instr
else if (combine_comparison_ordering(ctx, instr)) ;
else if (combine_constant_comparison_ordering(ctx, instr)) ;
else combine_salu_n2(ctx, instr);
+ } else if (instr->opcode == aco_opcode::v_and_b32) {
+ combine_and_subbrev(ctx, instr);
} else {
aco_opcode min, max, min3, max3, med3;
bool some_gfx9_only;
diff --git a/src/amd/compiler/tests/test_optimizer.cpp b/src/amd/compiler/tests/test_optimizer.cpp
index d28f2cb3a03..4bb5898e236 100644
--- a/src/amd/compiler/tests/test_optimizer.cpp
+++ b/src/amd/compiler/tests/test_optimizer.cpp
@@ -80,3 +80,45 @@ BEGIN_TEST(optimize.neg)
finish_opt_test();
}
END_TEST
+
+Temp create_subbrev_co(Operand op0, Operand op1, Operand op2)
+{
+ return bld.vop2_e64(aco_opcode::v_subbrev_co_u32, bld.def(v1), bld.hint_vcc(bld.def(bld.lm)), op0, op1, op2);
+}
+
+BEGIN_TEST(optimize.cndmask)
+ for (unsigned i = GFX9; i <= GFX10; i++) {
+ //>> v1: %a, s1: %b, s2: %c, s2: %_:exec = p_startpgm
+ if (!setup_cs("v1 s1 s2", (chip_class)i))
+ continue;
+
+ Temp subbrev;
+
+ //! v1: %res0 = v_cndmask_b32 0, %a, %c
+ //! p_unit_test 0, %res0
+ subbrev = create_subbrev_co(Operand(0u), Operand(0u), Operand(inputs[2]));
+ writeout(0, bld.vop2(aco_opcode::v_and_b32, bld.def(v1), inputs[0], subbrev));
+
+ //! v1: %res1 = v_cndmask_b32 0, 42, %c
+ //! p_unit_test 1, %res1
+ subbrev = create_subbrev_co(Operand(0u), Operand(0u), Operand(inputs[2]));
+ writeout(1, bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(42u), subbrev));
+
+ //~gfx9! v1: %subbrev, s2: %_ = v_subbrev_co_u32 0, 0, %c
+ //~gfx9! v1: %res2 = v_and_b32 %b, %subbrev
+ //~gfx10! v1: %res2 = v_cndmask_b32 0, %b, %c
+ //! p_unit_test 2, %res2
+ subbrev = create_subbrev_co(Operand(0u), Operand(0u), Operand(inputs[2]));
+ writeout(2, bld.vop2(aco_opcode::v_and_b32, bld.def(v1), inputs[1], subbrev));
+
+ //! v1: %subbrev1, s2: %_ = v_subbrev_co_u32 0, 0, %c
+ //! v1: %xor = v_xor_b32 %a, %subbrev1
+ //! v1: %res3 = v_cndmask_b32 0, %xor, %c
+ //! p_unit_test 3, %res3
+ subbrev = create_subbrev_co(Operand(0u), Operand(0u), Operand(inputs[2]));
+ Temp xor_a = bld.vop2(aco_opcode::v_xor_b32, bld.def(v1), inputs[0], subbrev);
+ writeout(3, bld.vop2(aco_opcode::v_and_b32, bld.def(v1), xor_a, subbrev));
+
+ finish_opt_test();
+ }
+END_TEST
More information about the mesa-commit
mailing list