Mesa (master): intel/fs: Add assert on the brw_STAGE_prog_data downcasts
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Mon Nov 16 21:52:51 UTC 2020
Module: Mesa
Branch: master
Commit: b3daf341d4d0f8f5f97f48b095b4ac3678b9f1f9
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b3daf341d4d0f8f5f97f48b095b4ac3678b9f1f9
Author: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>
Date: Tue Nov 10 13:11:31 2020 -0900
intel/fs: Add assert on the brw_STAGE_prog_data downcasts
Motivation is to detect earlier certain bugs that can occur when
missing a check for the stage before using the downcast.
Reviewed-by: Marcin Ślusarz <marcin.slusarz at intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7540>
---
src/intel/compiler/brw_compiler.h | 47 +++++++++++++++++++-----------
src/intel/compiler/brw_fs.cpp | 3 ++
src/intel/compiler/brw_shader.cpp | 2 ++
src/intel/compiler/brw_vec4.cpp | 2 ++
src/intel/compiler/brw_vec4_gs_visitor.cpp | 2 ++
src/intel/compiler/brw_vec4_tcs.cpp | 2 ++
6 files changed, 41 insertions(+), 17 deletions(-)
diff --git a/src/intel/compiler/brw_compiler.h b/src/intel/compiler/brw_compiler.h
index 347cc6ab2cf..e02409436b3 100644
--- a/src/intel/compiler/brw_compiler.h
+++ b/src/intel/compiler/brw_compiler.h
@@ -703,6 +703,8 @@ struct brw_stage_prog_data {
GLuint nr_params; /**< number of float params/constants */
GLuint nr_pull_params;
+ gl_shader_stage stage;
+
/* zero_push_reg is a bitfield which indicates what push registers (if any)
* should be zeroed by SW at the start of the shader. The corresponding
* push_reg_mask_param specifies the param index (in 32-bit units) where
@@ -1340,27 +1342,38 @@ union brw_any_prog_data {
struct brw_cs_prog_data cs;
};
-#define DEFINE_PROG_DATA_DOWNCAST(stage) \
-static inline struct brw_##stage##_prog_data * \
-brw_##stage##_prog_data(struct brw_stage_prog_data *prog_data) \
+#define DEFINE_PROG_DATA_DOWNCAST(STAGE, CHECK) \
+static inline struct brw_##STAGE##_prog_data * \
+brw_##STAGE##_prog_data(struct brw_stage_prog_data *prog_data) \
{ \
- return (struct brw_##stage##_prog_data *) prog_data; \
+ if (prog_data) \
+ assert(CHECK); \
+ return (struct brw_##STAGE##_prog_data *) prog_data; \
} \
-static inline const struct brw_##stage##_prog_data * \
-brw_##stage##_prog_data_const(const struct brw_stage_prog_data *prog_data) \
+static inline const struct brw_##STAGE##_prog_data * \
+brw_##STAGE##_prog_data_const(const struct brw_stage_prog_data *prog_data) \
{ \
- return (const struct brw_##stage##_prog_data *) prog_data; \
+ if (prog_data) \
+ assert(CHECK); \
+ return (const struct brw_##STAGE##_prog_data *) prog_data; \
}
-DEFINE_PROG_DATA_DOWNCAST(vue)
-DEFINE_PROG_DATA_DOWNCAST(vs)
-DEFINE_PROG_DATA_DOWNCAST(tcs)
-DEFINE_PROG_DATA_DOWNCAST(tes)
-DEFINE_PROG_DATA_DOWNCAST(gs)
-DEFINE_PROG_DATA_DOWNCAST(wm)
-DEFINE_PROG_DATA_DOWNCAST(cs)
-DEFINE_PROG_DATA_DOWNCAST(ff_gs)
-DEFINE_PROG_DATA_DOWNCAST(clip)
-DEFINE_PROG_DATA_DOWNCAST(sf)
+
+DEFINE_PROG_DATA_DOWNCAST(vs, prog_data->stage == MESA_SHADER_VERTEX)
+DEFINE_PROG_DATA_DOWNCAST(tcs, prog_data->stage == MESA_SHADER_TESS_CTRL)
+DEFINE_PROG_DATA_DOWNCAST(tes, prog_data->stage == MESA_SHADER_TESS_EVAL)
+DEFINE_PROG_DATA_DOWNCAST(gs, prog_data->stage == MESA_SHADER_GEOMETRY)
+DEFINE_PROG_DATA_DOWNCAST(wm, prog_data->stage == MESA_SHADER_FRAGMENT)
+DEFINE_PROG_DATA_DOWNCAST(cs, prog_data->stage == MESA_SHADER_COMPUTE)
+
+DEFINE_PROG_DATA_DOWNCAST(vue, prog_data->stage == MESA_SHADER_VERTEX ||
+ prog_data->stage == MESA_SHADER_TESS_CTRL ||
+ prog_data->stage == MESA_SHADER_TESS_EVAL ||
+ prog_data->stage == MESA_SHADER_GEOMETRY)
+
+/* These are not really brw_stage_prog_data. */
+DEFINE_PROG_DATA_DOWNCAST(ff_gs, true)
+DEFINE_PROG_DATA_DOWNCAST(clip, true)
+DEFINE_PROG_DATA_DOWNCAST(sf, true)
#undef DEFINE_PROG_DATA_DOWNCAST
struct brw_compile_stats {
diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp
index 6a77c3afd58..eda234c838f 100644
--- a/src/intel/compiler/brw_fs.cpp
+++ b/src/intel/compiler/brw_fs.cpp
@@ -8769,6 +8769,8 @@ brw_compile_fs(const struct brw_compiler *compiler, void *log_data,
struct brw_compile_stats *stats,
char **error_str)
{
+ prog_data->base.stage = MESA_SHADER_FRAGMENT;
+
const struct gen_device_info *devinfo = compiler->devinfo;
const unsigned max_subgroup_size = compiler->devinfo->gen >= 6 ? 32 : 16;
@@ -9133,6 +9135,7 @@ brw_compile_cs(const struct brw_compiler *compiler, void *log_data,
struct brw_compile_stats *stats,
char **error_str)
{
+ prog_data->base.stage = MESA_SHADER_COMPUTE;
prog_data->base.total_shared = nir->info.cs.shared_size;
/* Generate code for all the possible SIMD variants. */
diff --git a/src/intel/compiler/brw_shader.cpp b/src/intel/compiler/brw_shader.cpp
index dbe28748508..c44becfe0a1 100644
--- a/src/intel/compiler/brw_shader.cpp
+++ b/src/intel/compiler/brw_shader.cpp
@@ -1283,6 +1283,8 @@ brw_compile_tes(const struct brw_compiler *compiler,
const bool is_scalar = compiler->scalar_stage[MESA_SHADER_TESS_EVAL];
const unsigned *assembly;
+ prog_data->base.base.stage = MESA_SHADER_TESS_EVAL;
+
nir->info.inputs_read = key->inputs_read;
nir->info.patch_inputs_read = key->patch_inputs_read;
diff --git a/src/intel/compiler/brw_vec4.cpp b/src/intel/compiler/brw_vec4.cpp
index 8b97312ca20..d21c6750edf 100644
--- a/src/intel/compiler/brw_vec4.cpp
+++ b/src/intel/compiler/brw_vec4.cpp
@@ -2836,6 +2836,8 @@ brw_compile_vs(const struct brw_compiler *compiler, void *log_data,
struct brw_compile_stats *stats,
char **error_str)
{
+ prog_data->base.base.stage = MESA_SHADER_VERTEX;
+
const bool is_scalar = compiler->scalar_stage[MESA_SHADER_VERTEX];
brw_nir_apply_key(nir, compiler, &key->base, 8, is_scalar);
diff --git a/src/intel/compiler/brw_vec4_gs_visitor.cpp b/src/intel/compiler/brw_vec4_gs_visitor.cpp
index 3e0aba03083..2a1841c7875 100644
--- a/src/intel/compiler/brw_vec4_gs_visitor.cpp
+++ b/src/intel/compiler/brw_vec4_gs_visitor.cpp
@@ -598,6 +598,8 @@ brw_compile_gs(const struct brw_compiler *compiler, void *log_data,
const bool is_scalar = compiler->scalar_stage[MESA_SHADER_GEOMETRY];
+ prog_data->base.base.stage = MESA_SHADER_GEOMETRY;
+
/* The GLSL linker will have already matched up GS inputs and the outputs
* of prior stages. The driver does extend VS outputs in some cases, but
* only for legacy OpenGL or Gen4-5 hardware, neither of which offer
diff --git a/src/intel/compiler/brw_vec4_tcs.cpp b/src/intel/compiler/brw_vec4_tcs.cpp
index 2a4c379d217..5268e8b6cf6 100644
--- a/src/intel/compiler/brw_vec4_tcs.cpp
+++ b/src/intel/compiler/brw_vec4_tcs.cpp
@@ -370,6 +370,8 @@ brw_compile_tcs(const struct brw_compiler *compiler,
const bool is_scalar = compiler->scalar_stage[MESA_SHADER_TESS_CTRL];
const unsigned *assembly;
+ vue_prog_data->base.stage = MESA_SHADER_TESS_CTRL;
+
nir->info.outputs_written = key->outputs_written;
nir->info.patch_outputs_written = key->patch_outputs_written;
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