Mesa (master): ci: add list of expected failures for Sienna Cichlid

[GitLab Mirror]

Module: Mesa
Branch: master
Commit: 0678fdd983dfbc3f82671a66f6dbc7607f955e99
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=0678fdd983dfbc3f82671a66f6dbc7607f955e99

Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date:   Thu Nov 19 12:23:31 2020 +0100

ci: add list of expected failures for Sienna Cichlid

Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7686>

---

 .gitlab-ci/deqp-radv-sienna-cichlid-aco-fails.txt | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/.gitlab-ci/deqp-radv-sienna-cichlid-aco-fails.txt b/.gitlab-ci/deqp-radv-sienna-cichlid-aco-fails.txt
new file mode 100644
index 00000000000..b8df553dd26
--- /dev/null
+++ b/.gitlab-ci/deqp-radv-sienna-cichlid-aco-fails.txt
@@ -0,0 +1,9 @@
+dEQP-VK.api.copy_and_blit.core.resolve_image.whole_array_image.4_bit,Fail
+dEQP-VK.api.copy_and_blit.core.resolve_image.whole_array_image_one_region.4_bit,Fail
+dEQP-VK.api.copy_and_blit.core.resolve_image.whole_copy_before_resolving.4_bit,Fail
+dEQP-VK.api.copy_and_blit.dedicated_allocation.resolve_image.whole_array_image.4_bit,Fail
+dEQP-VK.api.copy_and_blit.dedicated_allocation.resolve_image.whole_array_image_one_region.4_bit,Fail
+dEQP-VK.api.copy_and_blit.dedicated_allocation.resolve_image.whole_copy_before_resolving.4_bit,Fail
+dEQP-VK.pipeline.blend.format.e5b9g9r9_ufloat_pack32.states.color_1mcc_1mdc_min_alpha_da_sc_sub-color_1mcc_sa_min_alpha_sa_ca_max-color_o_z_add_alpha_1mda_da_add-color_1mdc_sa_min_alpha_1mcc_sc_rsub,Fail
+dEQP-VK.pipeline.blend.format.e5b9g9r9_ufloat_pack32.states.color_o_1msa_add_alpha_o_1mda_max-color_da_1msa_sub_alpha_dc_sc_rsub-color_sc_ca_max_alpha_1mcc_sa_max-color_dc_ca_min_alpha_z_sc_rsub,Fail
+dEQP-VK.pipeline.blend.format.e5b9g9r9_ufloat_pack32.states.color_sa_z_sub_alpha_ca_cc_sub-color_sas_1msa_rsub_alpha_ca_da_sub-color_1mca_ca_min_alpha_1msc_1mcc_rsub-color_dc_da_sub_alpha_1mcc_1mda_add,Fail