Mesa (master): nir: allow for cheap intrinsics in nir_opt_peephole_select()

[GitLab Mirror]

Module: Mesa
Branch: master
Commit: 8d477baa4f917f502758268ade6590fef7a89d4e
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=8d477baa4f917f502758268ade6590fef7a89d4e

Author: Daniel Schürmann <daniel at schuermann.dev>
Date:   Tue Nov 19 17:24:34 2019 +0100

nir: allow for cheap intrinsics in nir_opt_peephole_select()

Also added nir_instr_type_ssa_undef for convenience.
Out of the added intrinsics, it seems that only load_helper_invocation
has an effect on tested games.

Totals from 446 (0.32% of 138013) affected shaders (RAVEN):
SGPRs: 17600 -> 17688 (+0.50%); split: -0.09%, +0.59%
VGPRs: 14140 -> 14312 (+1.22%); split: -0.03%, +1.24%
CodeSize: 1157696 -> 1131208 (-2.29%)
MaxWaves: 3430 -> 3427 (-0.09%)
Instrs: 220402 -> 214200 (-2.81%)
Cycles: 900776 -> 875752 (-2.78%)
VMEM: 160894 -> 180439 (+12.15%); split: +12.19%, -0.04%
SMEM: 19854 -> 20169 (+1.59%); split: +1.74%, -0.16%
VClause: 3597 -> 3604 (+0.19%)
SClause: 7258 -> 7248 (-0.14%); split: -0.15%, +0.01%
Copies: 17060 -> 16336 (-4.24%); split: -4.44%, +0.20%
Branches: 3995 -> 2518 (-36.97%)
PreSGPRs: 11972 -> 12148 (+1.47%); split: -0.13%, +1.60%

Reviewed-by: Rhys Perry <pendingchaos02 at gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2804>

---

 src/compiler/nir/nir_opt_peephole_select.c | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/src/compiler/nir/nir_opt_peephole_select.c b/src/compiler/nir/nir_opt_peephole_select.c
index be0f3081fad..2d7bc04a693 100644
--- a/src/compiler/nir/nir_opt_peephole_select.c
+++ b/src/compiler/nir/nir_opt_peephole_select.c
@@ -91,6 +91,27 @@ block_check_for_allowed_instrs(nir_block *block, unsigned *count,
          }
 
          case nir_intrinsic_load_uniform:
+         case nir_intrinsic_load_helper_invocation:
+         case nir_intrinsic_is_helper_invocation:
+         case nir_intrinsic_load_front_face:
+         case nir_intrinsic_load_view_index:
+         case nir_intrinsic_load_layer_id:
+         case nir_intrinsic_load_frag_coord:
+         case nir_intrinsic_load_sample_pos:
+         case nir_intrinsic_load_sample_id:
+         case nir_intrinsic_load_sample_mask_in:
+         case nir_intrinsic_load_vertex_id_zero_base:
+         case nir_intrinsic_load_first_vertex:
+         case nir_intrinsic_load_base_instance:
+         case nir_intrinsic_load_instance_id:
+         case nir_intrinsic_load_draw_id:
+         case nir_intrinsic_load_num_work_groups:
+         case nir_intrinsic_load_work_group_id:
+         case nir_intrinsic_load_local_invocation_id:
+         case nir_intrinsic_load_local_invocation_index:
+         case nir_intrinsic_load_subgroup_id:
+         case nir_intrinsic_load_subgroup_invocation:
+         case nir_intrinsic_load_num_subgroups:
             if (!alu_ok)
                return false;
             break;
@@ -104,6 +125,7 @@ block_check_for_allowed_instrs(nir_block *block, unsigned *count,
 
       case nir_instr_type_deref:
       case nir_instr_type_load_const:
+      case nir_instr_type_ssa_undef:
          break;
 
       case nir_instr_type_alu: {