Mesa (master): radv: Fix RB+ blending for VK_FORMAT_E5B9G9R9_UFLOAT_PACK32.

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Module: Mesa
Branch: master
Commit: 025cb90042ba62db8f4be6b612c8f5d2b6b3746b
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=025cb90042ba62db8f4be6b612c8f5d2b6b3746b

Author: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Date:   Sat Nov 21 20:58:37 2020 +0100

radv: Fix RB+ blending for VK_FORMAT_E5B9G9R9_UFLOAT_PACK32.

Fixes: e893102bcf5 ("radv: Add VK_FORMAT_E5B9G9R9_UFLOAT_PACK32 rendering support.")
Reviewed-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7716>

---

 .gitlab-ci/deqp-radv-sienna_cichlid-aco-fails.txt | 3 ---
 src/amd/vulkan/radv_cmd_buffer.c                  | 5 +++++
 2 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/.gitlab-ci/deqp-radv-sienna_cichlid-aco-fails.txt b/.gitlab-ci/deqp-radv-sienna_cichlid-aco-fails.txt
index b8df553dd26..b74873d9c7c 100644
--- a/.gitlab-ci/deqp-radv-sienna_cichlid-aco-fails.txt
+++ b/.gitlab-ci/deqp-radv-sienna_cichlid-aco-fails.txt
@@ -4,6 +4,3 @@ dEQP-VK.api.copy_and_blit.core.resolve_image.whole_copy_before_resolving.4_bit,F
 dEQP-VK.api.copy_and_blit.dedicated_allocation.resolve_image.whole_array_image.4_bit,Fail
 dEQP-VK.api.copy_and_blit.dedicated_allocation.resolve_image.whole_array_image_one_region.4_bit,Fail
 dEQP-VK.api.copy_and_blit.dedicated_allocation.resolve_image.whole_copy_before_resolving.4_bit,Fail
-dEQP-VK.pipeline.blend.format.e5b9g9r9_ufloat_pack32.states.color_1mcc_1mdc_min_alpha_da_sc_sub-color_1mcc_sa_min_alpha_sa_ca_max-color_o_z_add_alpha_1mda_da_add-color_1mdc_sa_min_alpha_1mcc_sc_rsub,Fail
-dEQP-VK.pipeline.blend.format.e5b9g9r9_ufloat_pack32.states.color_o_1msa_add_alpha_o_1mda_max-color_da_1msa_sub_alpha_dc_sc_rsub-color_sc_ca_max_alpha_1mcc_sa_max-color_dc_ca_min_alpha_z_sc_rsub,Fail
-dEQP-VK.pipeline.blend.format.e5b9g9r9_ufloat_pack32.states.color_sa_z_sub_alpha_ca_cc_sub-color_sas_1msa_rsub_alpha_ca_da_sub-color_1mca_ca_min_alpha_1msc_1mcc_rsub-color_dc_da_sub_alpha_1mcc_1mda_add,Fail
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 4ed317f91f9..9f8abad8ed6 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -1119,6 +1119,11 @@ radv_emit_rbplus_state(struct radv_cmd_buffer *cmd_buffer)
 			has_alpha = false;
 		}
 
+		/* The HW doesn't quite blend correctly with rgb9e5 if we disable the alpha
+		 * optimization, even though it has no alpha. */
+		if (has_rgb && format == V_028C70_COLOR_5_9_9_9)
+			has_alpha = true;
+
 		/* Disable value checking for disabled channels. */
 		if (!has_rgb)
 			sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);