Mesa (master): amd: Stub sections that don't have _WIN32 support
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Sat Nov 28 05:32:02 UTC 2020
Module: Mesa
Branch: master
Commit: 3ad8ac38c760732db87ff9809a049b0324804ff3
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3ad8ac38c760732db87ff9809a049b0324804ff3
Author: James Park <jpark37 at lagfreegames.com>
Date: Thu Nov 26 20:41:08 2020 -0800
amd: Stub sections that don't have _WIN32 support
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7791>
---
src/amd/common/ac_debug.c | 8 +++
src/amd/common/ac_gpu_info.c | 130 +++++++++++++++++++++++++++++++++++++-
src/amd/common/ac_shadowed_regs.c | 4 +-
3 files changed, 140 insertions(+), 2 deletions(-)
diff --git a/src/amd/common/ac_debug.c b/src/amd/common/ac_debug.c
index 5acf4928d0b..a4a16e231fe 100644
--- a/src/amd/common/ac_debug.c
+++ b/src/amd/common/ac_debug.c
@@ -639,6 +639,9 @@ void ac_parse_ib(FILE *f, uint32_t *ib, int num_dw, const int *trace_ids, unsign
bool ac_vm_fault_occured(enum chip_class chip_class, uint64_t *old_dmesg_timestamp,
uint64_t *out_addr)
{
+#ifdef _WIN32
+ return false;
+#else
char line[2000];
unsigned sec, usec;
int progress = 0;
@@ -733,6 +736,7 @@ bool ac_vm_fault_occured(enum chip_class chip_class, uint64_t *old_dmesg_timesta
*old_dmesg_timestamp = dmesg_timestamp;
return fault;
+#endif
}
static int compare_wave(const void *p1, const void *p2)
@@ -773,6 +777,9 @@ static int compare_wave(const void *p1, const void *p2)
unsigned ac_get_wave_info(enum chip_class chip_class,
struct ac_wave_info waves[AC_MAX_WAVES_PER_CHIP])
{
+#ifdef _WIN32
+ return 0;
+#else
char line[2000], cmd[128];
unsigned num_waves = 0;
@@ -808,4 +815,5 @@ unsigned ac_get_wave_info(enum chip_class chip_class,
pclose(p);
return num_waves;
+#endif
}
diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c
index 8e1f0388455..e07545deb97 100644
--- a/src/amd/common/ac_gpu_info.c
+++ b/src/amd/common/ac_gpu_info.c
@@ -31,9 +31,137 @@
#include "util/macros.h"
#include "util/u_math.h"
-#include <amdgpu.h>
#include <stdio.h>
+
+#ifdef _WIN32
+typedef struct _drmPciBusInfo {
+ uint16_t domain;
+ uint8_t bus;
+ uint8_t dev;
+ uint8_t func;
+} drmPciBusInfo, *drmPciBusInfoPtr;
+typedef struct _drmDevice {
+ union {
+ drmPciBusInfoPtr pci;
+ } businfo;
+} drmDevice, *drmDevicePtr;
+enum amdgpu_sw_info {
+ amdgpu_sw_info_address32_hi = 0,
+};
+typedef struct amdgpu_device *amdgpu_device_handle;
+typedef struct amdgpu_bo *amdgpu_bo_handle;
+struct amdgpu_bo_alloc_request {
+ uint64_t alloc_size;
+ uint64_t phys_alignment;
+ uint32_t preferred_heap;
+ uint64_t flags;
+};
+struct amdgpu_gds_resource_info {
+ uint32_t gds_gfx_partition_size;
+ uint32_t gds_total_size;
+};
+struct amdgpu_buffer_size_alignments {
+ uint64_t size_local;
+ uint64_t size_remote;
+};
+struct amdgpu_heap_info {
+ uint64_t heap_size;
+};
+struct amdgpu_gpu_info {
+ uint32_t asic_id;
+ uint32_t chip_external_rev;
+ uint32_t family_id;
+ uint64_t ids_flags;
+ uint64_t max_engine_clk;
+ uint64_t max_memory_clk;
+ uint32_t num_shader_engines;
+ uint32_t num_shader_arrays_per_engine;
+ uint32_t rb_pipes;
+ uint32_t enabled_rb_pipes_mask;
+ uint32_t gpu_counter_freq;
+ uint32_t mc_arb_ramcfg;
+ uint32_t gb_addr_cfg;
+ uint32_t gb_tile_mode[32];
+ uint32_t gb_macro_tile_mode[16];
+ uint32_t cu_bitmap[4][4];
+ uint32_t vram_type;
+ uint32_t vram_bit_width;
+ uint32_t ce_ram_size;
+ uint32_t vce_harvest_config;
+ uint32_t pci_rev_id;
+};
+int drmGetCap(int fd, uint64_t capability, uint64_t *value)
+{
+ return -EINVAL;
+}
+void drmFreeDevice(drmDevicePtr *device)
+{
+}
+int drmGetDevice2(int fd, uint32_t flags, drmDevicePtr *device)
+{
+ return -ENODEV;
+}
+int amdgpu_bo_alloc(amdgpu_device_handle dev,
+ struct amdgpu_bo_alloc_request *alloc_buffer,
+ amdgpu_bo_handle *buf_handle)
+{
+ return -EINVAL;
+}
+int amdgpu_bo_free(amdgpu_bo_handle buf_handle)
+{
+ return -EINVAL;
+}
+int amdgpu_query_buffer_size_alignment(amdgpu_device_handle dev,
+ struct amdgpu_buffer_size_alignments
+ *info)
+{
+ return -EINVAL;
+}
+int amdgpu_query_firmware_version(amdgpu_device_handle dev, unsigned fw_type,
+ unsigned ip_instance, unsigned index,
+ uint32_t *version, uint32_t *feature)
+{
+ return -EINVAL;
+}
+int amdgpu_query_hw_ip_info(amdgpu_device_handle dev, unsigned type,
+ unsigned ip_instance,
+ struct drm_amdgpu_info_hw_ip *info)
+{
+ return -EINVAL;
+}
+int amdgpu_query_heap_info(amdgpu_device_handle dev, uint32_t heap,
+ uint32_t flags, struct amdgpu_heap_info *info)
+{
+ return -EINVAL;
+}
+int amdgpu_query_gpu_info(amdgpu_device_handle dev,
+ struct amdgpu_gpu_info *info)
+{
+ return -EINVAL;
+}
+int amdgpu_query_info(amdgpu_device_handle dev, unsigned info_id,
+ unsigned size, void *value)
+{
+ return -EINVAL;
+}
+int amdgpu_query_sw_info(amdgpu_device_handle dev, enum amdgpu_sw_info info,
+ void *value)
+{
+ return -EINVAL;
+}
+int amdgpu_query_gds_info(amdgpu_device_handle dev,
+ struct amdgpu_gds_resource_info *gds_info)
+{
+ return -EINVAL;
+}
+const char *amdgpu_get_marketing_name(amdgpu_device_handle dev)
+{
+ return NULL;
+}
+#else
+#include <amdgpu.h>
#include <xf86drm.h>
+#endif
#define CIK_TILE_MODE_COLOR_2D 14
diff --git a/src/amd/common/ac_shadowed_regs.c b/src/amd/common/ac_shadowed_regs.c
index 77cab6a9044..538c5f8e483 100644
--- a/src/amd/common/ac_shadowed_regs.c
+++ b/src/amd/common/ac_shadowed_regs.c
@@ -3012,8 +3012,9 @@ void ac_print_shadowed_regs(const struct radeon_info *info)
const char *name = ac_get_register_name(info->chip_class, offset);
unsigned value = -1;
- char cmd[1024];
+#ifndef _WIN32
+ char cmd[1024];
snprintf(cmd, sizeof(cmd), "umr -r 0x%x", offset);
FILE *p = popen(cmd, "r");
if (p) {
@@ -3021,6 +3022,7 @@ void ac_print_shadowed_regs(const struct radeon_info *info)
assert(r == 1);
pclose(p);
}
+#endif
printf("0x%X %s = 0x%X\n", offset, name, value);
}
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