Mesa (master): radv: only mask 1 CU for GS/VS waves on GFX10.3

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Module: Mesa
Branch: master
Commit: bf36cfced183bac5bb5e2f8e564674071493bdad
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=bf36cfced183bac5bb5e2f8e564674071493bdad

Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date:   Wed Nov 25 08:16:14 2020 +0100

radv: only mask 1 CU for GS/VS waves on GFX10.3

Ported from Radeonsi and PAL.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7769>

---

 src/amd/vulkan/si_cmd_buffer.c | 16 +++++++++++-----
 1 file changed, 11 insertions(+), 5 deletions(-)

diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c
index ee521f3a880..c20a39a01bb 100644
--- a/src/amd/vulkan/si_cmd_buffer.c
+++ b/src/amd/vulkan/si_cmd_buffer.c
@@ -347,12 +347,18 @@ si_emit_graphics(struct radv_device *device,
 			} else {
 				late_alloc_wave64 = (num_cu_per_sh - 2) * 4;
 
-				/* CU2 & CU3 disabled because of the dual CU design */
-				cu_mask_vs = 0xfff3;
+				/* Gfx10: CU2 & CU3 must be disabled to
+				 * prevent a hw deadlock.  Others: CU1 must be
+				 * disabled to prevent a hw deadlock.
+				 *
+				 * The deadlock is caused by late alloc, which
+				 * usually increases performance.
+				 */
+				cu_mask_vs &= physical_device->rad_info.chip_class == GFX10 ?
+					      ~BITFIELD_RANGE(2, 2) : ~BITFIELD_RANGE(1, 1);
+
 				if (physical_device->use_ngg) {
-					cu_mask_gs = 0xfff3;
-				} else {
-					cu_mask_gs = 0xffff;
+					cu_mask_gs = cu_mask_vs;
 				}
 			}