Mesa (master): nir: Use the right argument order for load_scratch_base_ptr

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Module: Mesa
Branch: master
Commit: b70847a3894cff36c6a4bd1cc96d174e5920397e
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=b70847a3894cff36c6a4bd1cc96d174e5920397e

Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Mon Nov 30 10:41:35 2020 -0600

nir: Use the right argument order for load_scratch_base_ptr

Fixes: c9bcad25737 "nir: add generated intrinsic builders"
Reviewed-by: Rhys Perry <pendingchaos02 at gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7836>

---

 src/compiler/nir/nir_lower_io.c         | 4 ++--
 src/intel/compiler/brw_nir_rt_builder.h | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/compiler/nir/nir_lower_io.c b/src/compiler/nir/nir_lower_io.c
index 0eb4348286d..614163debec 100644
--- a/src/compiler/nir/nir_lower_io.c
+++ b/src/compiler/nir/nir_lower_io.c
@@ -880,11 +880,11 @@ build_addr_for_var(nir_builder *b, nir_variable *var,
       nir_ssa_def *base_addr;
       switch (var->data.mode) {
       case nir_var_shader_temp:
-         base_addr = nir_load_scratch_base_ptr(b, 0, num_comps, bit_size);
+         base_addr = nir_load_scratch_base_ptr(b, num_comps, bit_size, 0);
          break;
 
       case nir_var_function_temp:
-         base_addr = nir_load_scratch_base_ptr(b, 1, num_comps, bit_size);
+         base_addr = nir_load_scratch_base_ptr(b, num_comps, bit_size, 1);
          break;
 
       case nir_var_mem_constant:
diff --git a/src/intel/compiler/brw_nir_rt_builder.h b/src/intel/compiler/brw_nir_rt_builder.h
index dd53027fe03..2b4c545c819 100644
--- a/src/intel/compiler/brw_nir_rt_builder.h
+++ b/src/intel/compiler/brw_nir_rt_builder.h
@@ -36,7 +36,7 @@ brw_nir_rt_load_scratch(nir_builder *b, uint32_t offset, unsigned align,
                         unsigned num_components, unsigned bit_size)
 {
    nir_ssa_def *addr =
-      nir_iadd_imm(b, nir_load_scratch_base_ptr(b, 1, 1, 64), offset);
+      nir_iadd_imm(b, nir_load_scratch_base_ptr(b, 1, 64, 1), offset);
    return nir_load_global(b, addr, MIN2(align, BRW_BTD_STACK_ALIGN),
                           num_components, bit_size);
 }
@@ -46,7 +46,7 @@ brw_nir_rt_store_scratch(nir_builder *b, uint32_t offset, unsigned align,
                          nir_ssa_def *value, nir_component_mask_t write_mask)
 {
    nir_ssa_def *addr =
-      nir_iadd_imm(b, nir_load_scratch_base_ptr(b, 1, 1, 64), offset);
+      nir_iadd_imm(b, nir_load_scratch_base_ptr(b, 1, 64, 1), offset);
    nir_store_global(b, addr, MIN2(align, BRW_BTD_STACK_ALIGN),
                     value, write_mask);
 }