Mesa (master): isl: Allow CCS for 8bpp surfaces with 3+ miplevels

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Module: Mesa
Branch: master
Commit: 0d9216a7cbd11895e3b8c132f658225ccdeef478
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=0d9216a7cbd11895e3b8c132f658225ccdeef478

Author: Nanley Chery <nanley.g.chery at intel.com>
Date:   Fri Oct  9 11:25:53 2020 -0700

isl: Allow CCS for 8bpp surfaces with 3+ miplevels

I can't find a restriction for enabling CCS on these surfaces in recent
versions of the Bspec. Since I didn't cite my source, I'm not even sure
such a restriction existed in the first place.

Reviewed-by: Sagar Ghuge <sagar.ghuge at intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7085>

---

 src/intel/isl/isl.c | 11 -----------
 1 file changed, 11 deletions(-)

diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
index 1f3797122d4..313f0efe96a 100644
--- a/src/intel/isl/isl.c
+++ b/src/intel/isl/isl.c
@@ -1972,17 +1972,6 @@ isl_surf_supports_ccs(const struct isl_device *dev,
       if (isl_surf_usage_is_stencil(surf->usage) && surf->samples > 1)
          return false;
 
-      /* On Gen12, 8BPP surfaces cannot be compressed if any level is not
-       * 32Bx4row-aligned. For now, just reject the cases where alignment
-       * matters.
-       */
-      if (isl_format_get_layout(surf->format)->bpb == 8 && surf->levels >= 3) {
-         isl_finishme("%s:%s: CCS for 8BPP textures with 3+ miplevels is "
-                      "disabled, but support for more levels is possible.",
-                      __FILE__, __func__);
-         return false;
-      }
-
       /* On Gen12, all CCS-compressed surface pitches must be multiples of
        * 512B.
        */