Mesa (master): panfrost: add LDST_ADDRESS property to atomic ops

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Module: Mesa
Branch: master
Commit: 16664fc641801225878589f72ee3ae6f0cb28bac
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=16664fc641801225878589f72ee3ae6f0cb28bac

Author: Italo Nicola <italonicola at collabora.com>
Date:   Wed Aug 26 11:01:45 2020 +0000

panfrost: add LDST_ADDRESS property to atomic ops

Atomic ops have to encode the address of the variable it's writing to.
This property is used to align the address to 64-bit boundaries.

Signed-off-by: Italo Nicola <italonicola at collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig at collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6439>

---

 src/panfrost/midgard/midgard_ops.c | 42 +++++++++++++++++++-------------------
 1 file changed, 21 insertions(+), 21 deletions(-)

diff --git a/src/panfrost/midgard/midgard_ops.c b/src/panfrost/midgard/midgard_ops.c
index ef30523bc1a..2d70ed0c3ff 100644
--- a/src/panfrost/midgard/midgard_ops.c
+++ b/src/panfrost/midgard/midgard_ops.c
@@ -188,27 +188,27 @@ struct mir_ldst_op_props load_store_opcode_props[256] = {
         [midgard_op_ldst_perspective_division_z] = {"ldst_perspective_division_z", M32},
         [midgard_op_ldst_perspective_division_w] = {"ldst_perspective_division_w", M32},
 
-        [midgard_op_atomic_add]  = {"atomic_add",  M32 | LDST_SIDE_FX},
-        [midgard_op_atomic_and]  = {"atomic_and",  M32 | LDST_SIDE_FX},
-        [midgard_op_atomic_or]   = {"atomic_or",   M32 | LDST_SIDE_FX},
-        [midgard_op_atomic_xor]  = {"atomic_xor",  M32 | LDST_SIDE_FX},
-        [midgard_op_atomic_imin] = {"atomic_imin", M32 | LDST_SIDE_FX},
-        [midgard_op_atomic_umin] = {"atomic_umin", M32 | LDST_SIDE_FX},
-        [midgard_op_atomic_imax] = {"atomic_imax", M32 | LDST_SIDE_FX},
-        [midgard_op_atomic_umax] = {"atomic_umax", M32 | LDST_SIDE_FX},
-        [midgard_op_atomic_xchg] = {"atomic_xchg", M32 | LDST_SIDE_FX},
-        [midgard_op_atomic_cmpxchg] = {"atomic_cmpxchg", M32 | LDST_SIDE_FX},
-
-        [midgard_op_atomic_add64]  = {"atomic_add64",  M64 | LDST_SIDE_FX},
-        [midgard_op_atomic_and64]  = {"atomic_and64",  M64 | LDST_SIDE_FX},
-        [midgard_op_atomic_or64]   = {"atomic_or64",   M64 | LDST_SIDE_FX},
-        [midgard_op_atomic_xor64]  = {"atomic_xor64",  M64 | LDST_SIDE_FX},
-        [midgard_op_atomic_imin64] = {"atomic_imin64", M64 | LDST_SIDE_FX},
-        [midgard_op_atomic_umin64] = {"atomic_umin64", M64 | LDST_SIDE_FX},
-        [midgard_op_atomic_imax64] = {"atomic_imax64", M64 | LDST_SIDE_FX},
-        [midgard_op_atomic_umax64] = {"atomic_umax64", M64 | LDST_SIDE_FX},
-        [midgard_op_atomic_xchg64] = {"atomic_xchg64", M64 | LDST_SIDE_FX},
-        [midgard_op_atomic_cmpxchg64] = {"atomic_cmpxchg64", M64 | LDST_SIDE_FX},
+        [midgard_op_atomic_add]  = {"atomic_add",  M32 | LDST_SIDE_FX | LDST_ADDRESS},
+        [midgard_op_atomic_and]  = {"atomic_and",  M32 | LDST_SIDE_FX | LDST_ADDRESS},
+        [midgard_op_atomic_or]   = {"atomic_or",   M32 | LDST_SIDE_FX | LDST_ADDRESS},
+        [midgard_op_atomic_xor]  = {"atomic_xor",  M32 | LDST_SIDE_FX | LDST_ADDRESS},
+        [midgard_op_atomic_imin] = {"atomic_imin", M32 | LDST_SIDE_FX | LDST_ADDRESS},
+        [midgard_op_atomic_umin] = {"atomic_umin", M32 | LDST_SIDE_FX | LDST_ADDRESS},
+        [midgard_op_atomic_imax] = {"atomic_imax", M32 | LDST_SIDE_FX | LDST_ADDRESS},
+        [midgard_op_atomic_umax] = {"atomic_umax", M32 | LDST_SIDE_FX | LDST_ADDRESS},
+        [midgard_op_atomic_xchg] = {"atomic_xchg", M32 | LDST_SIDE_FX | LDST_ADDRESS},
+        [midgard_op_atomic_cmpxchg] = {"atomic_cmpxchg", M32 | LDST_SIDE_FX | LDST_ADDRESS},
+
+        [midgard_op_atomic_add64]  = {"atomic_add64",  M64 | LDST_SIDE_FX | LDST_ADDRESS},
+        [midgard_op_atomic_and64]  = {"atomic_and64",  M64 | LDST_SIDE_FX | LDST_ADDRESS},
+        [midgard_op_atomic_or64]   = {"atomic_or64",   M64 | LDST_SIDE_FX | LDST_ADDRESS},
+        [midgard_op_atomic_xor64]  = {"atomic_xor64",  M64 | LDST_SIDE_FX | LDST_ADDRESS},
+        [midgard_op_atomic_imin64] = {"atomic_imin64", M64 | LDST_SIDE_FX | LDST_ADDRESS},
+        [midgard_op_atomic_umin64] = {"atomic_umin64", M64 | LDST_SIDE_FX | LDST_ADDRESS},
+        [midgard_op_atomic_imax64] = {"atomic_imax64", M64 | LDST_SIDE_FX | LDST_ADDRESS},
+        [midgard_op_atomic_umax64] = {"atomic_umax64", M64 | LDST_SIDE_FX | LDST_ADDRESS},
+        [midgard_op_atomic_xchg64] = {"atomic_xchg64", M64 | LDST_SIDE_FX | LDST_ADDRESS},
+        [midgard_op_atomic_cmpxchg64] = {"atomic_cmpxchg64", M64 | LDST_SIDE_FX | LDST_ADDRESS},
 
         [midgard_op_ld_uchar]  = {"ld_uchar", M32 | LDST_ADDRESS},
         [midgard_op_ld_char]   = {"ld_char",   M32 | LDST_ADDRESS},