Mesa (master): radeonsi: don't lower indirect IO in GLSL

GitLab Mirror gitlab-mirror at kemper.freedesktop.org
Thu Sep 3 02:58:37 UTC 2020


Module: Mesa
Branch: master
Commit: 08ee72100fe22e067564cf71c25131771203dd36
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=08ee72100fe22e067564cf71c25131771203dd36

Author: Marek Olšák <marek.olsak at amd.com>
Date:   Sat Aug 22 08:41:23 2020 -0400

radeonsi: don't lower indirect IO in GLSL

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer at amd.com>
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6445>

---

 src/gallium/drivers/radeonsi/si_get.c | 22 ++--------------------
 1 file changed, 2 insertions(+), 20 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_get.c b/src/gallium/drivers/radeonsi/si_get.c
index 1ed24d992e0..45ccfaa964e 100644
--- a/src/gallium/drivers/radeonsi/si_get.c
+++ b/src/gallium/drivers/radeonsi/si_get.c
@@ -432,28 +432,10 @@ static int si_get_shader_param(struct pipe_screen *pscreen, enum pipe_shader_typ
    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
    case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
+   case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR: /* lowered in finalize_nir */
+   case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR: /* lowered in finalize_nir */
       return 1;
 
-   case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
-      /* TODO: Indirect indexing of GS inputs is unimplemented. */
-      if (shader == PIPE_SHADER_GEOMETRY)
-         return 0;
-
-      if (shader == PIPE_SHADER_VERTEX && !sscreen->llvm_has_working_vgpr_indexing)
-         return 0;
-
-      /* TCS and TES load inputs directly from LDS or offchip
-       * memory, so indirect indexing is always supported.
-       * PS has to support indirect indexing, because we can't
-       * lower that to TEMPs for INTERP instructions.
-       */
-      return 1;
-
-   case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
-      return sscreen->llvm_has_working_vgpr_indexing ||
-             /* TCS stores outputs directly to memory. */
-             shader == PIPE_SHADER_TESS_CTRL;
-
    /* Unsupported boolean features. */
    case PIPE_SHADER_CAP_FP16:
    case PIPE_SHADER_CAP_FP16_DERIVATIVES:



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