Mesa (master): intel/nir: Call validate_ssa_dominance at both ends of the NIR compile
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Tue Sep 8 19:58:33 UTC 2020
Module: Mesa
Branch: master
Commit: 3bd7c3c9dbde491173d7015e2168fc0f34d95bb8
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3bd7c3c9dbde491173d7015e2168fc0f34d95bb8
Author: Jason Ekstrand <jason at jlekstrand.net>
Date: Mon Jun 1 15:43:53 2020 -0500
intel/nir: Call validate_ssa_dominance at both ends of the NIR compile
This invokes it before we go into the optimization/lowering pass and
then right before we go out of SSA.
Reviewed-by: Daniel Schürmann <daniel at schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5288>
---
src/intel/compiler/brw_nir.c | 4 ++++
src/intel/vulkan/anv_pipeline.c | 1 +
2 files changed, 5 insertions(+)
diff --git a/src/intel/compiler/brw_nir.c b/src/intel/compiler/brw_nir.c
index d7b7551d739..335a8ef854d 100644
--- a/src/intel/compiler/brw_nir.c
+++ b/src/intel/compiler/brw_nir.c
@@ -685,6 +685,8 @@ brw_preprocess_nir(const struct brw_compiler *compiler, nir_shader *nir,
const bool is_scalar = compiler->scalar_stage[nir->info.stage];
+ nir_validate_ssa_dominance(nir, "before brw_preprocess_nir");
+
if (is_scalar) {
OPT(nir_lower_alu_to_scalar, NULL, NULL);
}
@@ -1053,6 +1055,8 @@ brw_postprocess_nir(nir_shader *nir, const struct brw_compiler *compiler,
nir_print_shader(nir, stderr);
}
+ nir_validate_ssa_dominance(nir, "before nir_convert_from_ssa");
+
OPT(nir_convert_from_ssa, true);
if (!is_scalar) {
diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c
index 664a916033b..a16137786bb 100644
--- a/src/intel/vulkan/anv_pipeline.c
+++ b/src/intel/vulkan/anv_pipeline.c
@@ -242,6 +242,7 @@ anv_shader_compile_to_nir(struct anv_device *device,
stage, entrypoint_name, &spirv_options, nir_options);
assert(nir->info.stage == stage);
nir_validate_shader(nir, "after spirv_to_nir");
+ nir_validate_ssa_dominance(nir, "after spirv_to_nir");
ralloc_steal(mem_ctx, nir);
free(spec_entries);
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