Mesa (master): Revert "radeonsi: set BIG_PAGE fields on gfx10.3"

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Module: Mesa
Branch: master
Commit: b23013db0aa6845d661c2da5d4003615b064e01f
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=b23013db0aa6845d661c2da5d4003615b064e01f

Author: Marek Olšák <marek.olsak at amd.com>
Date:   Mon Sep 14 20:59:36 2020 -0400

Revert "radeonsi: set BIG_PAGE fields on gfx10.3"

This reverts commit 430d384c311468c6180a1d67ed90bb74d4fe1c3b.

BIT_PAGE can't be set for GTT and we don't know if a buffer has been
evicted to GTT.

Fixes: 430d384c311468c6180a1d67ed90bb74d4fe1c3b

Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer at amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6722>

---

 src/gallium/drivers/radeonsi/si_pipe.h  |  2 --
 src/gallium/drivers/radeonsi/si_state.c | 24 +++---------------------
 2 files changed, 3 insertions(+), 23 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h
index f23865cec2b..355033c17e1 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -715,8 +715,6 @@ struct si_framebuffer {
    bool CB_has_shader_readable_metadata;
    bool DB_has_shader_readable_metadata;
    bool all_DCC_pipe_aligned;
-   bool color_big_page;
-   bool zs_big_page;
 };
 
 enum si_quant_mode
diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index 75507a30cc4..225efaec1bf 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -2703,8 +2703,6 @@ static void si_set_framebuffer_state(struct pipe_context *ctx,
    sctx->framebuffer.DB_has_shader_readable_metadata = false;
    sctx->framebuffer.all_DCC_pipe_aligned = true;
    sctx->framebuffer.min_bytes_per_pixel = 0;
-   sctx->framebuffer.color_big_page = true;
-   sctx->framebuffer.zs_big_page = true;
 
    for (i = 0; i < state->nr_cbufs; i++) {
       if (!state->cbufs[i])
@@ -2724,9 +2722,6 @@ static void si_set_framebuffer_state(struct pipe_context *ctx,
       sctx->framebuffer.spi_shader_col_format_blend_alpha |= surf->spi_shader_col_format_blend_alpha
                                                              << (i * 4);
 
-      sctx->framebuffer.color_big_page &=
-            tex->buffer.bo_alignment % (64 * 1024) == 0;
-
       if (surf->color_is_int8)
          sctx->framebuffer.color_is_int8 |= 1 << i;
       if (surf->color_is_int10)
@@ -2792,8 +2787,6 @@ static void si_set_framebuffer_state(struct pipe_context *ctx,
          si_init_depth_surface(sctx, surf);
       }
 
-      sctx->framebuffer.zs_big_page = zstex->buffer.bo_alignment % (64 * 1024) == 0;
-
       if (vi_tc_compat_htile_enabled(zstex, surf->base.u.tex.level, PIPE_MASK_ZS))
          sctx->framebuffer.DB_has_shader_readable_metadata = true;
 
@@ -3134,9 +3127,6 @@ static void si_emit_framebuffer_state(struct si_context *sctx)
       }
 
       if (sctx->chip_class >= GFX10) {
-         bool zs_big_page = sctx->chip_class >= GFX10_3 &&
-                            sctx->framebuffer.zs_big_page;
-
          radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
          radeon_set_context_reg(cs, R_02801C_DB_DEPTH_SIZE_XY, zb->db_depth_size);
 
@@ -3163,9 +3153,7 @@ static void si_emit_framebuffer_state(struct si_context *sctx)
                      S_02807C_ZPCPSD_WR_POLICY(V_02807C_CACHE_STREAM) |
                      S_02807C_Z_RD_POLICY(V_02807C_CACHE_NOA) |
                      S_02807C_S_RD_POLICY(V_02807C_CACHE_NOA) |
-                     S_02807C_HTILE_RD_POLICY(meta_read_policy) |
-                     S_02807C_Z_BIG_PAGE(zs_big_page) |
-                     S_02807C_S_BIG_PAGE(zs_big_page));
+                     S_02807C_HTILE_RD_POLICY(meta_read_policy));
       } else if (sctx->chip_class == GFX9) {
          radeon_set_context_reg_seq(cs, R_028014_DB_HTILE_DATA_BASE, 3);
          radeon_emit(cs, zb->db_htile_data_base); /* DB_HTILE_DATA_BASE */
@@ -3253,8 +3241,6 @@ static void si_emit_framebuffer_state(struct si_context *sctx)
                           S_028208_BR_X(state->width) | S_028208_BR_Y(state->height));
 
    if (nr_cbufs) {
-      bool color_big_page = sctx->chip_class >= GFX10_3 &&
-                            sctx->framebuffer.color_big_page;
       radeon_set_context_reg(cs, R_028410_CB_RMI_GL2_CACHE_CONTROL,
                              S_028410_CMASK_WR_POLICY(meta_write_policy) |
                              S_028410_FMASK_WR_POLICY(meta_write_policy) |
@@ -3263,9 +3249,7 @@ static void si_emit_framebuffer_state(struct si_context *sctx)
                              S_028410_CMASK_RD_POLICY(meta_read_policy) |
                              S_028410_FMASK_RD_POLICY(meta_read_policy) |
                              S_028410_DCC_RD_POLICY(meta_read_policy) |
-                             S_028410_COLOR_RD_POLICY(V_028410_CACHE_NOA) |
-                             S_028410_FMASK_BIG_PAGE(color_big_page) |
-                             S_028410_COLOR_BIG_PAGE(color_big_page));
+                             S_028410_COLOR_RD_POLICY(V_028410_CACHE_NOA));
    }
 
    if (sctx->screen->dfsm_allowed) {
@@ -3756,9 +3740,7 @@ static void gfx10_make_texture_descriptor(
    state[5] = S_00A014_ARRAY_PITCH(!!(type == V_008F1C_SQ_RSRC_IMG_3D && !sampler)) |
               S_00A014_MAX_MIP(res->nr_samples > 1 ? util_logbase2(res->nr_samples)
                                                    : tex->buffer.b.b.last_level) |
-              S_00A014_PERF_MOD(4) |
-              S_00A014_BIG_PAGE(screen->info.chip_class >= GFX10_3 &&
-                                tex->buffer.bo_alignment % (64 * 1024) == 0);
+              S_00A014_PERF_MOD(4);
    state[6] = 0;
    state[7] = 0;