Mesa (master): radeonsi: fix user fence GPU address

[GitLab Mirror]

Module: Mesa
Branch: master
Commit: 4656e682947621829f9297f01b2aaffb384bb762
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=4656e682947621829f9297f01b2aaffb384bb762

Author: Qiang Yu <yuq825 at gmail.com>
Date:   Fri Sep 18 20:03:46 2020 +0800

radeonsi: fix user fence GPU address

User fence should have 4 QWORD memory space, I updated its CPU address
but forgot to update GPU address.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3513
Fixes: 3d5bed0e883 "radeonsi: fix user fence space when MCBP is enabled"
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer at amd.com>
Signed-off-by: Qiang Yu <yuq825 at gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6776>

---

 src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
index 6abadf3cd9e..abfe4940541 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
@@ -973,7 +973,7 @@ amdgpu_cs_create(struct radeon_winsys_ctx *rwctx,
 
    struct amdgpu_cs_fence_info fence_info;
    fence_info.handle = cs->ctx->user_fence_bo;
-   fence_info.offset = cs->ring_type;
+   fence_info.offset = cs->ring_type * 4;
    amdgpu_cs_chunk_fence_info_to_data(&fence_info, (void*)&cs->fence_chunk);
 
    cs->main.ib_type = IB_MAIN;