Mesa (master): amd: add Dimgrey Cavefish support
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Tue Sep 22 17:08:21 UTC 2020
Module: Mesa
Branch: master
Commit: d7495bd123a6215f85a5b9a01e2c3ab5bc203c53
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d7495bd123a6215f85a5b9a01e2c3ab5bc203c53
Author: Marek Olšák <marek.olsak at amd.com>
Date: Mon Sep 16 21:41:08 2019 -0400
amd: add Dimgrey Cavefish support
Acked-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer at amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6820>
---
src/amd/addrlib/src/amdgpu_asic_addr.h | 2 ++
src/amd/addrlib/src/gfx10/gfx10addrlib.cpp | 6 ++++++
src/amd/common/ac_gpu_info.c | 2 ++
src/amd/common/amd_family.h | 1 +
src/amd/llvm/ac_llvm_util.c | 1 +
src/gallium/drivers/radeon/radeon_vcn_dec.c | 1 +
6 files changed, 13 insertions(+)
diff --git a/src/amd/addrlib/src/amdgpu_asic_addr.h b/src/amd/addrlib/src/amdgpu_asic_addr.h
index bef2ef78575..278c2a4d47f 100644
--- a/src/amd/addrlib/src/amdgpu_asic_addr.h
+++ b/src/amd/addrlib/src/amdgpu_asic_addr.h
@@ -99,6 +99,7 @@
#define AMDGPU_NAVI14_RANGE 0x14, 0x28
#define AMDGPU_SIENNA_CICHLID_RANGE 0x28, 0x32
#define AMDGPU_NAVY_FLOUNDER_RANGE 0x32, 0x3C
+#define AMDGPU_DIMGREY_CAVEFISH_RANGE 0x3C, 0x46
#define AMDGPU_EXPAND_FIX(x) x
#define AMDGPU_RANGE_HELPER(val, min, max) ((val >= min) && (val < max))
@@ -148,5 +149,6 @@
#define ASICREV_IS_NAVI14(r) ASICREV_IS(r, NAVI14)
#define ASICREV_IS_SIENNA_CICHLID(r) ASICREV_IS(r, SIENNA_CICHLID)
#define ASICREV_IS_NAVY_FLOUNDER(r) ASICREV_IS(r, NAVY_FLOUNDER)
+#define ASICREV_IS_DIMGREY_CAVEFISH(r) ASICREV_IS(r, DIMGREY_CAVEFISH)
#endif // _AMDGPU_ASIC_ADDR_H
diff --git a/src/amd/addrlib/src/gfx10/gfx10addrlib.cpp b/src/amd/addrlib/src/gfx10/gfx10addrlib.cpp
index 8116c3b169c..bc12a2c79b7 100644
--- a/src/amd/addrlib/src/gfx10/gfx10addrlib.cpp
+++ b/src/amd/addrlib/src/gfx10/gfx10addrlib.cpp
@@ -933,6 +933,12 @@ ChipFamily Gfx10Lib::HwlConvertChipFamily(
m_settings.supportRbPlus = 1;
m_settings.dccUnsup3DSwDis = 0;
}
+
+ if (ASICREV_IS_DIMGREY_CAVEFISH(chipRevision))
+ {
+ m_settings.supportRbPlus = 1;
+ m_settings.dccUnsup3DSwDis = 0;
+ }
break;
default:
ADDR_ASSERT(!"Unknown chip family");
diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c
index 770737a7ed4..468bc375676 100644
--- a/src/amd/common/ac_gpu_info.c
+++ b/src/amd/common/ac_gpu_info.c
@@ -400,6 +400,7 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info,
identify_chip(NAVI14);
identify_chip(SIENNA_CICHLID);
identify_chip(NAVY_FLOUNDER);
+ identify_chip(DIMGREY_CAVEFISH);
break;
}
@@ -706,6 +707,7 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info,
case CHIP_NAVI12:
case CHIP_SIENNA_CICHLID:
case CHIP_NAVY_FLOUNDER:
+ case CHIP_DIMGREY_CAVEFISH:
pc_lines = 1024;
break;
case CHIP_NAVI14:
diff --git a/src/amd/common/amd_family.h b/src/amd/common/amd_family.h
index 475cb835b3c..a1395a36de0 100644
--- a/src/amd/common/amd_family.h
+++ b/src/amd/common/amd_family.h
@@ -105,6 +105,7 @@ enum radeon_family
CHIP_NAVI14,
CHIP_SIENNA_CICHLID,
CHIP_NAVY_FLOUNDER,
+ CHIP_DIMGREY_CAVEFISH,
CHIP_LAST,
};
diff --git a/src/amd/llvm/ac_llvm_util.c b/src/amd/llvm/ac_llvm_util.c
index 8e220ba6853..0685e984038 100644
--- a/src/amd/llvm/ac_llvm_util.c
+++ b/src/amd/llvm/ac_llvm_util.c
@@ -176,6 +176,7 @@ const char *ac_get_llvm_processor_name(enum radeon_family family)
return "gfx1012";
case CHIP_SIENNA_CICHLID:
case CHIP_NAVY_FLOUNDER:
+ case CHIP_DIMGREY_CAVEFISH:
return "gfx1030";
default:
return "";
diff --git a/src/gallium/drivers/radeon/radeon_vcn_dec.c b/src/gallium/drivers/radeon/radeon_vcn_dec.c
index 51333749fa9..9254367d9c3 100644
--- a/src/gallium/drivers/radeon/radeon_vcn_dec.c
+++ b/src/gallium/drivers/radeon/radeon_vcn_dec.c
@@ -1614,6 +1614,7 @@ struct pipe_video_codec *radeon_create_decoder(struct pipe_context *context,
case CHIP_ARCTURUS:
case CHIP_SIENNA_CICHLID:
case CHIP_NAVY_FLOUNDER:
+ case CHIP_DIMGREY_CAVEFISH:
dec->reg.data0 = RDECODE_VCN2_5_GPCOM_VCPU_DATA0;
dec->reg.data1 = RDECODE_VCN2_5_GPCOM_VCPU_DATA1;
dec->reg.cmd = RDECODE_VCN2_5_GPCOM_VCPU_CMD;
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