Mesa (master): radeonsi/tmz: add tmz variant for sctx::tess_rings
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Thu Sep 24 15:06:53 UTC 2020
Module: Mesa
Branch: master
Commit: 8e2768bbfb1b0e9d70bb5a4d0267c6eb387d1c30
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=8e2768bbfb1b0e9d70bb5a4d0267c6eb387d1c30
Author: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer at amd.com>
Date: Thu Jul 23 16:54:08 2020 +0200
radeonsi/tmz: add tmz variant for sctx::tess_rings
tess_rings must be encrypted when used in a secure job so this commit
introduces a tess_rings_tmz resource.
The cs_preamble_state doesn't contain the tess_rings address anymore since
it can change. The tess_rings related registers go in a separate preamble.
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6049>
---
src/gallium/drivers/radeonsi/si_gfx_cs.c | 7 +++++-
src/gallium/drivers/radeonsi/si_pipe.c | 5 +++++
src/gallium/drivers/radeonsi/si_pipe.h | 3 +++
src/gallium/drivers/radeonsi/si_state_draw.c | 3 ++-
src/gallium/drivers/radeonsi/si_state_shaders.c | 30 ++++++++++++++++++++++---
5 files changed, 43 insertions(+), 5 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_gfx_cs.c b/src/gallium/drivers/radeonsi/si_gfx_cs.c
index 235b00021e9..d52a1e3e605 100644
--- a/src/gallium/drivers/radeonsi/si_gfx_cs.c
+++ b/src/gallium/drivers/radeonsi/si_gfx_cs.c
@@ -387,6 +387,7 @@ void si_set_tracked_regs_to_clear_state(struct si_context *ctx)
void si_begin_new_gfx_cs(struct si_context *ctx, bool first_cs)
{
+ bool is_secure = ctx->ws->cs_is_secure(ctx->gfx_cs);
if (ctx->is_debug)
si_begin_gfx_cs_debug(ctx);
@@ -426,7 +427,8 @@ void si_begin_new_gfx_cs(struct si_context *ctx, bool first_cs)
}
if (ctx->tess_rings) {
- radeon_add_to_buffer_list(ctx, ctx->gfx_cs, si_resource(ctx->tess_rings),
+ radeon_add_to_buffer_list(ctx, ctx->gfx_cs,
+ unlikely(is_secure) ? si_resource(ctx->tess_rings_tmz) : si_resource(ctx->tess_rings),
RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RINGS);
}
@@ -438,6 +440,9 @@ void si_begin_new_gfx_cs(struct si_context *ctx, bool first_cs)
/* The CS initialization should be emitted before everything else. */
if (ctx->cs_preamble_state)
si_pm4_emit(ctx, ctx->cs_preamble_state);
+ if (ctx->cs_preamble_tess_rings)
+ si_pm4_emit(ctx, unlikely(is_secure) ? ctx->cs_preamble_tess_rings_tmz :
+ ctx->cs_preamble_tess_rings);
if (ctx->cs_preamble_gs_rings)
si_pm4_emit(ctx, ctx->cs_preamble_gs_rings);
diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c
index 0a91ca4a2f0..9fa148dff9f 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -189,6 +189,7 @@ static void si_destroy_context(struct pipe_context *context)
pipe_resource_reference(&sctx->esgs_ring, NULL);
pipe_resource_reference(&sctx->gsvs_ring, NULL);
pipe_resource_reference(&sctx->tess_rings, NULL);
+ pipe_resource_reference(&sctx->tess_rings_tmz, NULL);
pipe_resource_reference(&sctx->null_const_buf.buffer, NULL);
pipe_resource_reference(&sctx->sample_pos_buffer, NULL);
si_resource_reference(&sctx->border_color_buffer, NULL);
@@ -201,6 +202,10 @@ static void si_destroy_context(struct pipe_context *context)
if (sctx->cs_preamble_state)
si_pm4_free_state(sctx, sctx->cs_preamble_state, ~0);
+ if (sctx->cs_preamble_tess_rings)
+ si_pm4_free_state(sctx, sctx->cs_preamble_tess_rings, ~0);
+ if (sctx->cs_preamble_tess_rings_tmz)
+ si_pm4_free_state(sctx, sctx->cs_preamble_tess_rings_tmz, ~0);
if (sctx->cs_preamble_gs_rings)
si_pm4_free_state(sctx, sctx->cs_preamble_gs_rings, ~0);
for (i = 0; i < ARRAY_SIZE(sctx->vgt_shader_config); i++)
diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h
index 55143899b29..c5d87b514a0 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -1022,6 +1022,8 @@ struct si_context {
/* Precomputed states. */
struct si_pm4_state *cs_preamble_state;
+ struct si_pm4_state *cs_preamble_tess_rings;
+ struct si_pm4_state *cs_preamble_tess_rings_tmz;
struct si_pm4_state *cs_preamble_gs_rings;
bool cs_preamble_has_vgt_flush;
struct si_pm4_state *vgt_shader_config[SI_NUM_VGT_STAGES_STATES];
@@ -1063,6 +1065,7 @@ struct si_context {
struct pipe_resource *esgs_ring;
struct pipe_resource *gsvs_ring;
struct pipe_resource *tess_rings;
+ struct pipe_resource *tess_rings_tmz;
union pipe_color_union *border_color_table; /* in CPU memory, any endian */
struct si_resource *border_color_buffer;
union pipe_color_union *border_color_map; /* in VRAM (slow access), little endian */
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c
index 6ac271cf2ee..8c93c3e5549 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -215,7 +215,8 @@ static void si_emit_derived_tess_state(struct si_context *sctx, const struct pip
assert(num_tcs_input_cp <= 32);
assert(num_tcs_output_cp <= 32);
- uint64_t ring_va = si_resource(sctx->tess_rings)->gpu_address;
+ uint64_t ring_va = (unlikely(sctx->ws->cs_is_secure(sctx->gfx_cs)) ?
+ si_resource(sctx->tess_rings_tmz) : si_resource(sctx->tess_rings))->gpu_address;
assert((ring_va & u_bit_consecutive(0, 19)) == 0);
tcs_in_layout = S_VS_STATE_LS_OUT_PATCH_SIZE(input_patch_size / 4) |
diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c b/src/gallium/drivers/radeonsi/si_state_shaders.c
index 8e10c9a35d7..ee252ac6b02 100644
--- a/src/gallium/drivers/radeonsi/si_state_shaders.c
+++ b/src/gallium/drivers/radeonsi/si_state_shaders.c
@@ -3701,11 +3701,20 @@ static void si_init_tess_factor_ring(struct si_context *sctx)
if (!sctx->tess_rings)
return;
+ if (sctx->screen->info.has_tmz_support) {
+ sctx->tess_rings_tmz = pipe_aligned_buffer_create(
+ sctx->b.screen,
+ PIPE_RESOURCE_FLAG_ENCRYPTED | SI_RESOURCE_FLAG_32BIT | SI_RESOURCE_FLAG_DRIVER_INTERNAL,
+ PIPE_USAGE_DEFAULT,
+ sctx->screen->tess_offchip_ring_size + sctx->screen->tess_factor_ring_size, 1 << 19);
+ }
+
uint64_t factor_va =
si_resource(sctx->tess_rings)->gpu_address + sctx->screen->tess_offchip_ring_size;
if (sctx->shadowed_regs) {
/* These registers will be shadowed, so set them only once. */
+ /* TODO: tmz + shadowed_regs support */
struct radeon_cmdbuf *cs = sctx->gfx_cs;
assert(sctx->chip_class >= GFX7);
@@ -3747,11 +3756,26 @@ static void si_init_tess_factor_ring(struct si_context *sctx)
si_pm4_set_reg(sctx->cs_preamble_state, R_03093C_VGT_HS_OFFCHIP_PARAM,
sctx->screen->vgt_hs_offchip_param);
} else {
- si_pm4_set_reg(sctx->cs_preamble_state, R_008988_VGT_TF_RING_SIZE,
+ struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
+
+ si_pm4_set_reg(pm4, R_008988_VGT_TF_RING_SIZE,
S_008988_SIZE(sctx->screen->tess_factor_ring_size / 4));
- si_pm4_set_reg(sctx->cs_preamble_state, R_0089B8_VGT_TF_MEMORY_BASE, factor_va >> 8);
- si_pm4_set_reg(sctx->cs_preamble_state, R_0089B0_VGT_HS_OFFCHIP_PARAM,
+ si_pm4_set_reg(pm4, R_0089B8_VGT_TF_MEMORY_BASE, factor_va >> 8);
+ si_pm4_set_reg(pm4, R_0089B0_VGT_HS_OFFCHIP_PARAM,
sctx->screen->vgt_hs_offchip_param);
+ sctx->cs_preamble_tess_rings = pm4;
+
+ if (sctx->screen->info.has_tmz_support) {
+ pm4 = CALLOC_STRUCT(si_pm4_state);
+ uint64_t factor_va_tmz =
+ si_resource(sctx->tess_rings_tmz)->gpu_address + sctx->screen->tess_offchip_ring_size;
+ si_pm4_set_reg(pm4, R_008988_VGT_TF_RING_SIZE,
+ S_008988_SIZE(sctx->screen->tess_factor_ring_size / 4));
+ si_pm4_set_reg(pm4, R_0089B8_VGT_TF_MEMORY_BASE, factor_va_tmz >> 8);
+ si_pm4_set_reg(pm4, R_0089B0_VGT_HS_OFFCHIP_PARAM,
+ sctx->screen->vgt_hs_offchip_param);
+ sctx->cs_preamble_tess_rings_tmz = pm4;
+ }
}
/* Flush the context to re-emit the cs_preamble state.
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