Mesa (master): amd/tmz: move uses_secure_bos to radeon_winsys
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Thu Sep 24 15:06:53 UTC 2020
Module: Mesa
Branch: master
Commit: 90b98c06493f8a9759e5496d5ec91fb60edf7b92
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=90b98c06493f8a9759e5496d5ec91fb60edf7b92
Author: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer at amd.com>
Date: Mon Jul 27 12:24:27 2020 +0200
amd/tmz: move uses_secure_bos to radeon_winsys
This allows to inline radeon_uses_secure_bos calls and reduce CPU overhead.
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6049>
---
src/gallium/drivers/radeon/radeon_winsys.h | 10 +++++++++-
src/gallium/drivers/radeonsi/si_compute.c | 2 +-
src/gallium/drivers/radeonsi/si_cp_dma.c | 2 +-
src/gallium/drivers/radeonsi/si_dma_cs.c | 4 ++--
src/gallium/drivers/radeonsi/si_gfx_cs.c | 2 +-
src/gallium/drivers/radeonsi/si_state_draw.c | 2 +-
src/gallium/winsys/amdgpu/drm/amdgpu_bo.c | 10 ++++++++--
src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 1 -
src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c | 7 -------
src/gallium/winsys/amdgpu/drm/amdgpu_winsys.h | 1 -
src/gallium/winsys/radeon/drm/radeon_drm_winsys.c | 6 ------
11 files changed, 23 insertions(+), 24 deletions(-)
diff --git a/src/gallium/drivers/radeon/radeon_winsys.h b/src/gallium/drivers/radeon/radeon_winsys.h
index 26d897b741b..3919e9fb232 100644
--- a/src/gallium/drivers/radeon/radeon_winsys.h
+++ b/src/gallium/drivers/radeon/radeon_winsys.h
@@ -252,6 +252,10 @@ struct radeon_winsys {
* The screen object this winsys was created for
*/
struct pipe_screen *screen;
+ /**
+ * Has the application created at least one TMZ buffer.
+ */
+ const bool uses_secure_bos;
/**
* Decrement the winsys reference count.
@@ -693,7 +697,6 @@ struct radeon_winsys {
/**
* Secure context
*/
- bool (*ws_uses_secure_bo)(struct radeon_winsys *ws);
bool (*cs_is_secure)(struct radeon_cmdbuf *cs);
};
@@ -714,6 +717,11 @@ static inline void radeon_emit_array(struct radeon_cmdbuf *cs, const uint32_t *v
cs->current.cdw += count;
}
+static inline bool radeon_uses_secure_bos(struct radeon_winsys* ws)
+{
+ return ws->uses_secure_bos;
+}
+
enum radeon_heap
{
RADEON_HEAP_VRAM_NO_CPU_ACCESS,
diff --git a/src/gallium/drivers/radeonsi/si_compute.c b/src/gallium/drivers/radeonsi/si_compute.c
index 23a65308813..ee28f82a165 100644
--- a/src/gallium/drivers/radeonsi/si_compute.c
+++ b/src/gallium/drivers/radeonsi/si_compute.c
@@ -848,7 +848,7 @@ static void si_launch_grid(struct pipe_context *ctx, const struct pipe_grid_info
si_need_gfx_cs_space(sctx);
/* If we're using a secure context, determine if cs must be secure or not */
- if (unlikely(sctx->ws->ws_uses_secure_bo(sctx->ws))) {
+ if (unlikely(radeon_uses_secure_bos(sctx->ws))) {
bool secure = si_compute_resources_check_encrypted(sctx);
if (secure != sctx->ws->cs_is_secure(sctx->gfx_cs)) {
si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW |
diff --git a/src/gallium/drivers/radeonsi/si_cp_dma.c b/src/gallium/drivers/radeonsi/si_cp_dma.c
index 71e3bdb8bde..90073b6d334 100644
--- a/src/gallium/drivers/radeonsi/si_cp_dma.c
+++ b/src/gallium/drivers/radeonsi/si_cp_dma.c
@@ -338,7 +338,7 @@ void si_cp_dma_copy_buffer(struct si_context *sctx, struct pipe_resource *dst,
}
/* TMZ handling */
- if (unlikely(sctx->ws->ws_uses_secure_bo(sctx->ws) &&
+ if (unlikely(radeon_uses_secure_bos(sctx->ws) &&
!(user_flags & SI_CPDMA_SKIP_TMZ))) {
bool secure = src && (si_resource(src)->flags & RADEON_FLAG_ENCRYPTED);
assert(!secure || (!dst || (si_resource(dst)->flags & RADEON_FLAG_ENCRYPTED)));
diff --git a/src/gallium/drivers/radeonsi/si_dma_cs.c b/src/gallium/drivers/radeonsi/si_dma_cs.c
index d5d0e892989..db9b5deb335 100644
--- a/src/gallium/drivers/radeonsi/si_dma_cs.c
+++ b/src/gallium/drivers/radeonsi/si_dma_cs.c
@@ -75,7 +75,7 @@ void si_sdma_clear_buffer(struct si_context *sctx, struct pipe_resource *dst, ui
if (!cs || dst->flags & PIPE_RESOURCE_FLAG_SPARSE ||
sctx->screen->debug_flags & DBG(NO_SDMA_CLEARS) ||
- unlikely(sctx->ws->ws_uses_secure_bo(sctx->ws))) {
+ unlikely(radeon_uses_secure_bos(sctx->ws))) {
sctx->b.clear_buffer(&sctx->b, dst, offset, size, &clear_value, 4);
return;
}
@@ -233,7 +233,7 @@ void si_need_dma_space(struct si_context *ctx, unsigned num_dw, struct si_resour
si_flush_gfx_cs(ctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
bool use_secure_cmd = false;
- if (unlikely(ctx->ws->ws_uses_secure_bo(ctx->ws))) {
+ if (unlikely(radeon_uses_secure_bos(ctx->ws))) {
if (src && src->flags & RADEON_FLAG_ENCRYPTED) {
assert(!dst || (dst->flags & RADEON_FLAG_ENCRYPTED));
use_secure_cmd = true;
diff --git a/src/gallium/drivers/radeonsi/si_gfx_cs.c b/src/gallium/drivers/radeonsi/si_gfx_cs.c
index 7efa3f08aa9..81d936805fe 100644
--- a/src/gallium/drivers/radeonsi/si_gfx_cs.c
+++ b/src/gallium/drivers/radeonsi/si_gfx_cs.c
@@ -394,7 +394,7 @@ void si_begin_new_gfx_cs(struct si_context *ctx, bool first_cs)
{
bool is_secure = false;
- if (unlikely(ctx->ws->ws_uses_secure_bo(ctx->ws))) {
+ if (unlikely(radeon_uses_secure_bos(ctx->ws))) {
/* Disable features that don't work with TMZ:
* - primitive discard
*/
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c
index 8c93c3e5549..7983f81239b 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -2039,7 +2039,7 @@ static void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *i
si_need_gfx_cs_space(sctx);
/* If we're using a secure context, determine if cs must be secure or not */
- if (unlikely(sctx->ws->ws_uses_secure_bo(sctx->ws))) {
+ if (unlikely(radeon_uses_secure_bos(sctx->ws))) {
bool secure = si_gfx_resources_check_encrypted(sctx);
if (secure != sctx->ws->cs_is_secure(sctx->gfx_cs)) {
si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW |
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
index 4a8c0e42d74..f2cb3e56c2d 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
@@ -525,8 +525,14 @@ static struct amdgpu_winsys_bo *amdgpu_create_bo(struct amdgpu_winsys *ws,
ws->info.has_tmz_support) {
request.flags |= AMDGPU_GEM_CREATE_ENCRYPTED;
- if (!(flags & RADEON_FLAG_DRIVER_INTERNAL))
- ws->uses_secure_bos = true;
+ if (!(flags & RADEON_FLAG_DRIVER_INTERNAL)) {
+ struct amdgpu_screen_winsys *sws_iter;
+ simple_mtx_lock(&ws->sws_list_lock);
+ for (sws_iter = ws->sws_list; sws_iter; sws_iter = sws_iter->next) {
+ *((bool*) &sws_iter->base.uses_secure_bos) = true;
+ }
+ simple_mtx_unlock(&ws->sws_list_lock);
+ }
}
r = amdgpu_bo_alloc(ws->dev, &request, &buf_handle);
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
index ded4c57f5e9..e07d2c4b9b4 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
@@ -1657,7 +1657,6 @@ static void amdgpu_cs_submit_ib(void *job, int thread_index)
num_chunks++;
if (cs->secure) {
- assert(ws->uses_secure_bos);
cs->ib[IB_PREAMBLE].flags |= AMDGPU_IB_FLAGS_SECURE;
cs->ib[IB_MAIN].flags |= AMDGPU_IB_FLAGS_SECURE;
} else {
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c b/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
index 9f0724047ab..d554ea5a67c 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
@@ -327,12 +327,6 @@ static bool kms_handle_equals(const void *a, const void *b)
return a == b;
}
-static bool amdgpu_ws_uses_secure_bo(struct radeon_winsys *rws)
-{
- struct amdgpu_winsys *ws = amdgpu_winsys(rws);
- return ws->uses_secure_bos;
-}
-
static bool amdgpu_cs_is_secure(struct radeon_cmdbuf *rcs)
{
struct amdgpu_cs *cs = amdgpu_cs(rcs);
@@ -512,7 +506,6 @@ amdgpu_winsys_create(int fd, const struct pipe_screen_config *config,
ws->base.query_value = amdgpu_query_value;
ws->base.read_registers = amdgpu_read_registers;
ws->base.pin_threads_to_L3_cache = amdgpu_pin_threads_to_L3_cache;
- ws->base.ws_uses_secure_bo = amdgpu_ws_uses_secure_bo;
ws->base.cs_is_secure = amdgpu_cs_is_secure;
amdgpu_bo_init_functions(ws);
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.h b/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.h
index 874e5c56afa..981189f5e77 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.h
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.h
@@ -85,7 +85,6 @@ struct amdgpu_winsys {
bool debug_all_bos;
bool reserve_vmid;
bool zero_all_vram_allocs;
- bool uses_secure_bos;
/* List of all allocated buffers */
simple_mtx_t global_bo_list_lock;
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
index 4e83c3ccc58..b9a092d9ae4 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
@@ -803,11 +803,6 @@ static void radeon_pin_threads_to_L3_cache(struct radeon_winsys *ws,
}
}
-static bool radeon_ws_uses_secure_bo(struct radeon_winsys* ws)
-{
- return false;
-}
-
static bool radeon_cs_is_secure(struct radeon_cmdbuf* cs)
{
return false;
@@ -884,7 +879,6 @@ radeon_drm_winsys_create(int fd, const struct pipe_screen_config *config,
ws->base.cs_request_feature = radeon_cs_request_feature;
ws->base.query_value = radeon_query_value;
ws->base.read_registers = radeon_read_registers;
- ws->base.ws_uses_secure_bo = radeon_ws_uses_secure_bo;
ws->base.cs_is_secure = radeon_cs_is_secure;
radeon_drm_bo_init_functions(ws);
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