Mesa (master): nir: set system_values_read for all intrinsics

[GitLab Mirror]

Module: Mesa
Branch: master
Commit: 7b108e6ac405525eacf24291f72732e7c918d527
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=7b108e6ac405525eacf24291f72732e7c918d527

Author: Marek Olšák <marek.olsak at amd.com>
Date:   Fri Sep 11 19:33:26 2020 -0400

nir: set system_values_read for all intrinsics

Reviewed-by: Eric Anholt <eric at anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6758>

---

 src/compiler/nir/nir.c             |  6 +++
 src/compiler/nir/nir_gather_info.c | 79 ++++++++++++++++++++++++++++++++------
 2 files changed, 74 insertions(+), 11 deletions(-)

diff --git a/src/compiler/nir/nir.c b/src/compiler/nir/nir.c
index e9e21e61e8a..99d11871b9a 100644
--- a/src/compiler/nir/nir.c
+++ b/src/compiler/nir/nir.c
@@ -2238,6 +2238,12 @@ nir_system_value_from_intrinsic(nir_intrinsic_op intrin)
       return SYSTEM_VALUE_WORK_DIM;
    case nir_intrinsic_load_user_data_amd:
       return SYSTEM_VALUE_USER_DATA_AMD;
+   case nir_intrinsic_load_barycentric_model:
+      return SYSTEM_VALUE_BARYCENTRIC_PULL_MODEL;
+   case nir_intrinsic_load_gs_header_ir3:
+      return SYSTEM_VALUE_GS_HEADER_IR3;
+   case nir_intrinsic_load_tcs_header_ir3:
+      return SYSTEM_VALUE_TCS_HEADER_IR3;
    default:
       unreachable("intrinsic doesn't produce a system value");
    }
diff --git a/src/compiler/nir/nir_gather_info.c b/src/compiler/nir/nir_gather_info.c
index 0f0fff09b3e..1780d3e1c6b 100644
--- a/src/compiler/nir/nir_gather_info.c
+++ b/src/compiler/nir/nir_gather_info.c
@@ -418,35 +418,92 @@ gather_intrinsic_info(nir_intrinsic_instr *instr, nir_shader *shader,
       }
       break;
 
-   case nir_intrinsic_load_draw_id:
-   case nir_intrinsic_load_frag_coord:
-   case nir_intrinsic_load_point_coord:
-   case nir_intrinsic_load_line_coord:
-   case nir_intrinsic_load_front_face:
+   case nir_intrinsic_load_subgroup_size:
+   case nir_intrinsic_load_subgroup_invocation:
+   case nir_intrinsic_load_subgroup_eq_mask:
+   case nir_intrinsic_load_subgroup_ge_mask:
+   case nir_intrinsic_load_subgroup_gt_mask:
+   case nir_intrinsic_load_subgroup_le_mask:
+   case nir_intrinsic_load_subgroup_lt_mask:
+   case nir_intrinsic_load_num_subgroups:
+   case nir_intrinsic_load_subgroup_id:
    case nir_intrinsic_load_vertex_id:
+   case nir_intrinsic_load_instance_id:
    case nir_intrinsic_load_vertex_id_zero_base:
    case nir_intrinsic_load_base_vertex:
    case nir_intrinsic_load_first_vertex:
    case nir_intrinsic_load_is_indexed_draw:
    case nir_intrinsic_load_base_instance:
-   case nir_intrinsic_load_instance_id:
+   case nir_intrinsic_load_draw_id:
+   case nir_intrinsic_load_invocation_id:
+   case nir_intrinsic_load_frag_coord:
+   case nir_intrinsic_load_point_coord:
+   case nir_intrinsic_load_line_coord:
+   case nir_intrinsic_load_front_face:
    case nir_intrinsic_load_sample_id:
    case nir_intrinsic_load_sample_pos:
    case nir_intrinsic_load_sample_mask_in:
+   case nir_intrinsic_load_helper_invocation:
+   case nir_intrinsic_load_color0:
+   case nir_intrinsic_load_color1:
+   case nir_intrinsic_load_tess_coord:
+   case nir_intrinsic_load_patch_vertices_in:
    case nir_intrinsic_load_primitive_id:
-   case nir_intrinsic_load_invocation_id:
+   case nir_intrinsic_load_tess_level_outer:
+   case nir_intrinsic_load_tess_level_inner:
+   case nir_intrinsic_load_tess_level_outer_default:
+   case nir_intrinsic_load_tess_level_inner_default:
    case nir_intrinsic_load_local_invocation_id:
    case nir_intrinsic_load_local_invocation_index:
+   case nir_intrinsic_load_global_invocation_id:
+   case nir_intrinsic_load_base_global_invocation_id:
+   case nir_intrinsic_load_global_invocation_index:
    case nir_intrinsic_load_work_group_id:
    case nir_intrinsic_load_num_work_groups:
-   case nir_intrinsic_load_tess_coord:
-   case nir_intrinsic_load_tess_level_outer:
-   case nir_intrinsic_load_tess_level_inner:
-   case nir_intrinsic_load_patch_vertices_in:
+   case nir_intrinsic_load_local_group_size:
+   case nir_intrinsic_load_work_dim:
+   case nir_intrinsic_load_user_data_amd:
+   case nir_intrinsic_load_view_index:
+   case nir_intrinsic_load_barycentric_model:
+   case nir_intrinsic_load_gs_header_ir3:
+   case nir_intrinsic_load_tcs_header_ir3:
       shader->info.system_values_read |=
          (1ull << nir_system_value_from_intrinsic(instr->intrinsic));
       break;
 
+   case nir_intrinsic_load_barycentric_pixel:
+      if (nir_intrinsic_interp_mode(instr) == INTERP_MODE_SMOOTH ||
+          nir_intrinsic_interp_mode(instr) == INTERP_MODE_NONE) {
+         shader->info.system_values_read |=
+            BITFIELD64_BIT(SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL);
+      } else if (nir_intrinsic_interp_mode(instr) == INTERP_MODE_NOPERSPECTIVE) {
+         shader->info.system_values_read |=
+            BITFIELD64_BIT(SYSTEM_VALUE_BARYCENTRIC_LINEAR_PIXEL);
+      }
+      break;
+
+   case nir_intrinsic_load_barycentric_centroid:
+      if (nir_intrinsic_interp_mode(instr) == INTERP_MODE_SMOOTH ||
+          nir_intrinsic_interp_mode(instr) == INTERP_MODE_NONE) {
+         shader->info.system_values_read |=
+            BITFIELD64_BIT(SYSTEM_VALUE_BARYCENTRIC_PERSP_CENTROID);
+      } else if (nir_intrinsic_interp_mode(instr) == INTERP_MODE_NOPERSPECTIVE) {
+         shader->info.system_values_read |=
+            BITFIELD64_BIT(SYSTEM_VALUE_BARYCENTRIC_LINEAR_CENTROID);
+      }
+      break;
+
+   case nir_intrinsic_load_barycentric_sample:
+      if (nir_intrinsic_interp_mode(instr) == INTERP_MODE_SMOOTH ||
+          nir_intrinsic_interp_mode(instr) == INTERP_MODE_NONE) {
+         shader->info.system_values_read |=
+            BITFIELD64_BIT(SYSTEM_VALUE_BARYCENTRIC_PERSP_SAMPLE);
+      } else if (nir_intrinsic_interp_mode(instr) == INTERP_MODE_NOPERSPECTIVE) {
+         shader->info.system_values_read |=
+            BITFIELD64_BIT(SYSTEM_VALUE_BARYCENTRIC_LINEAR_SAMPLE);
+      }
+      break;
+
    case nir_intrinsic_quad_broadcast:
    case nir_intrinsic_quad_swap_horizontal:
    case nir_intrinsic_quad_swap_vertical: