Mesa (master): 36 new commits

Fri Apr 2 12:30:16 UTC 2021

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=5e4d31f64600ef7421dd655381ff2297a5005cec
Author: Marek Olšák <marek.olsak at amd.com>
Date:   Fri Mar 19 15:48:16 2021 -0400

    ac/surface/tests: move shareable code into ac_surface_test_common.h
    
    Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer at amd.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=b3e6514984592cb79c705462f30c9525c681981b
Author: Marek Olšák <marek.olsak at amd.com>
Date:   Wed Mar 24 02:47:12 2021 -0400

    radeonsi: don't use CP DMA for clears/copies except for very small ones
    
    The current compute shaders are much faster.
    
    Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer at amd.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=64cbab5348c3342c231e69cc2fd91acf66aa5387
Author: Marek Olšák <marek.olsak at amd.com>
Date:   Sat Mar 20 20:05:03 2021 -0400

    radeonsi: turn the loops over color buffers into while loops in si_clear
    
    NULL color buffers are not set in "buffers" here.
    
    Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer at amd.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=5ba77c4a5d4d303e779979930c38501fd5297c1e
Author: Marek Olšák <marek.olsak at amd.com>
Date:   Sun Mar 21 11:12:39 2021 -0400

    radeonsi: unset PIPE_CLEAR_* flags for non-existent buffers
    
    Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer at amd.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=0580d4c1a25b75616d1b8732624bf63a27a929a9
Author: Marek Olšák <marek.olsak at amd.com>
Date:   Sat Mar 20 01:00:11 2021 -0400

    radeonsi: enable HTILE with mipmapping on gfx9+
    
    Everything seems to be there except fast clears.
    
    Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer at amd.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=4e35eb1d699ebacad14dce2ff8d9992e3c06def2
Author: Marek Olšák <marek.olsak at amd.com>
Date:   Sat Mar 20 00:59:50 2021 -0400

    radeonsi: set better default depth clear value
    
    Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer at amd.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=3345e32de71fc15150233b34310430362ee33d31
Author: Marek Olšák <marek.olsak at amd.com>
Date:   Sat Mar 20 00:10:57 2021 -0400

    radeonsi: group and parallelize all clears in si_texture_create_object
    
    This reduces aux_context flushes significantly.
    
    Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer at amd.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=cb6e1c7c117e224e5576091cdbe98e3dc14684f5
Author: Marek Olšák <marek.olsak at amd.com>
Date:   Fri Mar 19 20:45:08 2021 -0400

    radeonsi: add num_layers variable into si_do_fast_color_clear
    
    in preparation for the next commit
    
    Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer at amd.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=1936a046b1074bf5145bee7183ebdfeb9ed6db7d
Author: Marek Olšák <marek.olsak at amd.com>
Date:   Fri Mar 19 20:43:59 2021 -0400

    radeonsi: return success/failure from si_alloc_separate_cmask
    
    Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer at amd.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=8cd61d124876c307266f291f0ce5e9d2fede7058
Author: Marek Olšák <marek.olsak at amd.com>
Date:   Fri Mar 19 18:56:16 2021 -0400

    radeonsi: parallelize CMASK and DCC clears
    
    Clearing 8 RTs with both DCC and CMASK caused 16 synchronized clears where
    we also did 16 times WAIT_REG_MEM for CB flushes that were 15 times
    useless.
    
    Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer at amd.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=d0f06e5c4744878bc0416f4b20ee83241d9658f5
Author: Marek Olšák <marek.olsak at amd.com>
Date:   Mon Mar 15 21:22:55 2021 -0400

    radeonsi: remove si_screen::dcc_msaa_allowed
    
    Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer at amd.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=4707dc6a648bb4156d9b39021b5a3f029d9cc866
Author: Marek Olšák <marek.olsak at amd.com>
Date:   Mon Mar 15 21:20:13 2021 -0400

    radeonsi: determine accurately whether the framebuffer state has DCC MSAA
    
    We only need to check storage samples, which is what affects DCC.
    
    Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer at amd.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=933df6729646aefdfcb926ee2dc6dcf157fb0dfb
Author: Marek Olšák <marek.olsak at amd.com>
Date:   Fri Mar 19 20:42:14 2021 -0400

    ac/surface: add CMASK info for level 0
    
    Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer at amd.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=b3e7c77f136636c56535a86890dd134b843a26bb
Author: Marek Olšák <marek.olsak at amd.com>
Date:   Sun Mar 21 13:00:51 2021 -0400

    amd: fix parsing the last dword of DMA_DATA packets
    
    It was parsing it as SQ_WAVE_GPR_ALLOC instead of COMMAND.
    Change the offset to an odd number to work around it.
    
    Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer at amd.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=95940459be65b0a106a0b705e31607c71a3893bf
Author: Marek Olšák <marek.olsak at amd.com>
Date:   Sun Mar 21 19:59:37 2021 -0400

    radeonsi: pack the variable block size in one SGPR, 10 bits per component
    
    The side effect of this is that the compute copy image shader now has
    enough free user SGPRs that it passes the src image via user SGPRs,
    resulting in lower wave lifetime.
    
    Previous copy shader:
        s_load_dwordx8
        image_load
        s_load_dwordx8
        s_waitcnt
        image_store
    
    Current copy shader:
        image_load
        s_load_dwordx8
        s_waitcnt
        image_store
    
    Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer at amd.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=034c1e4845db67c19230d6f5877c9322d4013989
Author: Marek Olšák <marek.olsak at amd.com>
Date:   Sun Mar 21 19:57:09 2021 -0400

    radeonsi: decrease the maximum variable block size
    
    to allow packing the block size in 1 user SGPR with 10 bits per component,
    so that block sizes such as 512x1x1 fit in there.
    
    Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer at amd.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=ad71ef9326f1b6ad5a31ae73deb35d99602b767d
Author: Marek Olšák <marek.olsak at amd.com>
Date:   Sun Mar 21 19:39:09 2021 -0400

    radeonsi: don't use a constant buffer for the copy_image compute shader
    
    just use user SGPRs and 16-bit values for the x,y,z coordinates.
    
    Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer at amd.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=5701baa34b8f9de6b0dec95373e208942662d858
Author: Marek Olšák <marek.olsak at amd.com>
Date:   Sun Mar 21 17:36:22 2021 -0400

    radeonsi: don't use constbuf and set cache policy for 12-byte clear shader
    
    This removes the constant buffer and sets the cache policy like other
    compute shaders.
    
    Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer at amd.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=7d14eb623b0ff8c241ab477eeebdc447e25ccda2
Author: Marek Olšák <marek.olsak at amd.com>
Date:   Tue Mar 16 08:58:54 2021 -0400

    radeonsi: return false from si_is_format_supported instead of NULL
    
    Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer at amd.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=c53261645deca271522367e4af40393ff152eaee
Author: Marek Olšák <marek.olsak at amd.com>
Date:   Sun Mar 21 15:26:17 2021 -0400

    radeonsi: add SI_CONTEXT_PFP_SYNC_ME to skip syncing PFP for image operations
    
    DCC/CMASK/HTILE clears will not set this. We could do a better job
    at not setting this in other cases too
    
    Image copies also don't set this.
    
    Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer at amd.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=4fb1b7b2d80678dd8701005a058389d782dce112
Author: Marek Olšák <marek.olsak at amd.com>
Date:   Sun Mar 21 15:18:52 2021 -0400

    radeonsi: use the optimal packet order before draw packets for VS flushes too
    
    Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer at amd.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=b1a73ec99bd6612d289b445e1679b4aaa36e832a
Author: Marek Olšák <marek.olsak at amd.com>
Date:   Sun Mar 21 14:23:30 2021 -0400

    radeonsi: rename and apply SI_OP_CPDMA_SKIP_CACHE_FLUSH to compute as well
    
    Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer at amd.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=419e05d5f64d8be6bf34af8f44a0766e12c1d70c
Author: Marek Olšák <marek.olsak at amd.com>
Date:   Fri Mar 19 23:51:32 2021 -0400

    radeonsi: don't do an L2 flush in compute_do_clear_or_copy if we're not syncing
    
    Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer at amd.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=aed881e34ee3ccff0ad597f9869738df94479610
Author: Marek Olšák <marek.olsak at amd.com>
Date:   Fri Mar 19 23:35:43 2021 -0400

    radeonsi: reduce syncing in si_compute_expand_fmask when it's already idle
    
    Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer at amd.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=5c827bde2920dcc46ee2b2b06d1b7ed5af4076ed
Author: Marek Olšák <marek.olsak at amd.com>
Date:   Fri Mar 19 23:34:03 2021 -0400

    radeonsi: reduce syncing for initializing new buffers
    
    Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer at amd.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=207bafd4dd8f6d4df827cb39232f202a12c6b33d
Author: Marek Olšák <marek.olsak at amd.com>
Date:   Fri Mar 19 23:33:16 2021 -0400

    radeonsi: reduce syncing in si_dcc_decompress
    
    Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer at amd.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=7e2b5ce722453157f2c8c891c5c7863700d7aaf4
Author: Marek Olšák <marek.olsak at amd.com>
Date:   Fri Mar 19 23:20:48 2021 -0400

    radeonsi: set compute/cpdma sync flags in the outermost caller
    
    This allows us to control syncing everywhere.
    
    Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer at amd.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=a4ad08b455971d0b1cb15bcd705e316ef93d8763
Author: Marek Olšák <marek.olsak at amd.com>
Date:   Fri Mar 19 23:12:55 2021 -0400

    radeonsi: inline clear_buffer in si_screen_clear_buffer
    
    We'll add a new parameter there.
    
    Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer at amd.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=1af99a28a0bad7e7a1c7abc45eee27635eadbb32
Author: Marek Olšák <marek.olsak at amd.com>
Date:   Fri Mar 19 22:30:55 2021 -0400

    radeonsi: merge CP DMA flags with internal compute flags
    
    Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer at amd.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=dd5e9af78ff2753c9d01554bc45eff150ae029ee
Author: Marek Olšák <marek.olsak at amd.com>
Date:   Fri Mar 19 18:39:23 2021 -0400

    radeonsi: remove unused SI_CP_DMA_SKIP_* definitions
    
    The existing uses had no effect.
    
    Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer at amd.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=938dc0e291b00994639c613ad7db58ed0af05d6b
Author: Marek Olšák <marek.olsak at amd.com>
Date:   Fri Mar 19 22:17:38 2021 -0400

    radeonsi: rename internal compute sync flags
    
    Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer at amd.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=69ff9c16bbbc5d549606cb9f93550034893d394a
Author: Marek Olšák <marek.olsak at amd.com>
Date:   Fri Mar 19 18:48:04 2021 -0400

    radeonsi: never set DISABLE_WR_CONFIRM for CP DMA clears and copies
    
    Only prefetches set it. Unsynchronized clears and copies shouldn't set it
    because syncing later wouldn't wait for the writes.
    
    Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer at amd.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=28d065d3e5b32c19d20c1f3e71d7f28cb75c52bd
Author: Marek Olšák <marek.olsak at amd.com>
Date:   Fri Mar 19 17:54:08 2021 -0400

    radeonsi: don't insert start/stop pipeline stat events if it has no effect
    
    Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer at amd.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=cb59cae04c32c9ffaedd16e91d96fabbe7c9e3ea
Author: Marek Olšák <marek.olsak at amd.com>
Date:   Fri Mar 19 17:41:59 2021 -0400

    radeonsi: set the clear/copy cache policy based on L2 cache size
    
    This matches the intent.
    
    Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer at amd.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=8ea685dfc0d31fe0eeb127f3cb13307f34bc163b
Author: Marek Olšák <marek.olsak at amd.com>
Date:   Sun Mar 28 08:48:19 2021 -0400

    radeonsi: disable sparse buffers on gfx7-8
    
    Cc: 20.3 21.0 <mesa-stable at lists.freedesktop.org>
    Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer at amd.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=ac78b12e2307565adff436e101b5a8dba61a64b3
Author: Marek Olšák <marek.olsak at amd.com>
Date:   Sun Mar 28 07:46:25 2021 -0400

    ac/llvm: don't set unsupported xnack options to fix LLVM crashes on gfx6-8
    
    LLVM prints an error if xnack is unsupported and it uses a global stream
    object that is not thread-safe. Since Mesa uses multiple threads to compile
    shaders, there is a small chance that it will crash.
    
    Just don't set any xnack options to use LLVM defaults.
    
    Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4439
    
    Cc: 20.3 21.0 <mesa-stable at lists.freedesktop.org>
    Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer at amd.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795>