Mesa (master): intel: Rename ISL_DEV_GEN to ISL_GFX_VER
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Fri Apr 2 18:41:11 UTC 2021
Module: Mesa
Branch: master
Commit: cc422fa4983af5b0cc0afc37c284fd14fd92d817
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=cc422fa4983af5b0cc0afc37c284fd14fd92d817
Author: Anuj Phogat <anuj.phogat at gmail.com>
Date: Mon Mar 29 13:17:58 2021 -0700
intel: Rename ISL_DEV_GEN to ISL_GFX_VER
Commands used to do the changes:
export SEARCH_PATH="src/intel src/gallium/drivers/iris src/mesa/drivers/dri/i965"
grep -E "ISL_DEV_GEN" -rIl $SEARCH_PATH | xargs sed -ie "s/ISL_DEV_GEN/ISL_GFX_VER/g"
Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9936>
---
src/intel/blorp/blorp_blit.c | 2 +-
src/intel/blorp/blorp_clear.c | 18 +++---
src/intel/isl/isl.c | 116 +++++++++++++++++++-------------------
src/intel/isl/isl.h | 18 +++---
src/intel/isl/isl_gen4.c | 2 +-
src/intel/isl/isl_gen6.c | 2 +-
src/intel/isl/isl_gen7.c | 20 +++----
src/intel/isl/isl_gen8.c | 2 +-
src/intel/isl/isl_storage_image.c | 4 +-
9 files changed, 92 insertions(+), 92 deletions(-)
diff --git a/src/intel/blorp/blorp_blit.c b/src/intel/blorp/blorp_blit.c
index 6d0a6df84ae..6340117815d 100644
--- a/src/intel/blorp/blorp_blit.c
+++ b/src/intel/blorp/blorp_blit.c
@@ -2421,7 +2421,7 @@ get_copy_format_for_bpb(const struct isl_device *isl_dev, unsigned bpb)
* the table below is for RGB -> RGBA blits and so we will never have any
* UNORM/UINT mismatch.
*/
- if (ISL_DEV_GEN(isl_dev) >= 9) {
+ if (ISL_GFX_VER(isl_dev) >= 9) {
switch (bpb) {
case 8: return ISL_FORMAT_R8_UINT;
case 16: return ISL_FORMAT_R8G8_UINT;
diff --git a/src/intel/blorp/blorp_clear.c b/src/intel/blorp/blorp_clear.c
index beaeda1e51d..b131886e4d5 100644
--- a/src/intel/blorp/blorp_clear.c
+++ b/src/intel/blorp/blorp_clear.c
@@ -620,7 +620,7 @@ blorp_clear_stencil_as_rgba(struct blorp_batch *batch,
* We have to use RGBA16_UINT on SNB.
*/
enum isl_format wide_format;
- if (ISL_DEV_GEN(batch->blorp->isl_dev) <= 6) {
+ if (ISL_GFX_VER(batch->blorp->isl_dev) <= 6) {
wide_format = ISL_FORMAT_R16G16B16A16_UINT;
/* For RGBA16_UINT, we need to mask the stencil value otherwise, we risk
@@ -690,7 +690,7 @@ blorp_clear_depth_stencil(struct blorp_batch *batch,
params.x1 = x1;
params.y1 = y1;
- if (ISL_DEV_GEN(batch->blorp->isl_dev) == 6) {
+ if (ISL_GFX_VER(batch->blorp->isl_dev) == 6) {
/* For some reason, Sandy Bridge gets occlusion queries wrong if we
* don't have a shader. In particular, it records samples even though
* we disable statistics in 3DSTATE_WM. Give it the usual clear shader
@@ -896,7 +896,7 @@ blorp_hiz_clear_depth_stencil(struct blorp_batch *batch,
params.snapshot_type = INTEL_SNAPSHOT_HIZ_CLEAR;
/* This requires WM_HZ_OP which only exists on gen8+ */
- assert(ISL_DEV_GEN(batch->blorp->isl_dev) >= 8);
+ assert(ISL_GFX_VER(batch->blorp->isl_dev) >= 8);
params.hiz_op = ISL_AUX_OP_FAST_CLEAR;
/* From BSpec: 3DSTATE_WM_HZ_OP_BODY >> Full Surface Depth and Stencil Clear
@@ -1089,13 +1089,13 @@ blorp_ccs_resolve(struct blorp_batch *batch,
assert(aux_fmtl->txc == ISL_TXC_CCS);
unsigned x_scaledown, y_scaledown;
- if (ISL_DEV_GEN(batch->blorp->isl_dev) >= 12) {
+ if (ISL_GFX_VER(batch->blorp->isl_dev) >= 12) {
x_scaledown = aux_fmtl->bw * 8;
y_scaledown = aux_fmtl->bh * 4;
- } else if (ISL_DEV_GEN(batch->blorp->isl_dev) >= 9) {
+ } else if (ISL_GFX_VER(batch->blorp->isl_dev) >= 9) {
x_scaledown = aux_fmtl->bw * 8;
y_scaledown = aux_fmtl->bh * 8;
- } else if (ISL_DEV_GEN(batch->blorp->isl_dev) >= 8) {
+ } else if (ISL_GFX_VER(batch->blorp->isl_dev) >= 8) {
x_scaledown = aux_fmtl->bw * 8;
y_scaledown = aux_fmtl->bh * 16;
} else {
@@ -1272,7 +1272,7 @@ blorp_ccs_ambiguate(struct blorp_batch *batch,
struct blorp_surf *surf,
uint32_t level, uint32_t layer)
{
- if (ISL_DEV_GEN(batch->blorp->isl_dev) >= 10) {
+ if (ISL_GFX_VER(batch->blorp->isl_dev) >= 10) {
/* On gen10 and above, we have a hardware resolve op for this */
return blorp_ccs_resolve(batch, surf, level, layer, 1,
surf->surf->format, ISL_AUX_OP_AMBIGUATE);
@@ -1282,7 +1282,7 @@ blorp_ccs_ambiguate(struct blorp_batch *batch,
blorp_params_init(¶ms);
params.snapshot_type = INTEL_SNAPSHOT_CCS_AMBIGUATE;
- assert(ISL_DEV_GEN(batch->blorp->isl_dev) >= 7);
+ assert(ISL_GFX_VER(batch->blorp->isl_dev) >= 7);
const struct isl_format_layout *aux_fmtl =
isl_format_get_layout(surf->aux_surf->format);
@@ -1332,7 +1332,7 @@ blorp_ccs_ambiguate(struct blorp_batch *batch,
* clear in units of Y-tiled cache lines.
*/
uint32_t x_offset_cl, y_offset_cl, width_cl, height_cl;
- if (ISL_DEV_GEN(batch->blorp->isl_dev) >= 8) {
+ if (ISL_GFX_VER(batch->blorp->isl_dev) >= 8) {
/* From the Sky Lake PRM Vol. 12 in the section on planes:
*
* "The Color Control Surface (CCS) contains the compression status
diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
index 0acf3cb0ff9..b3c2921de92 100644
--- a/src/intel/isl/isl.c
+++ b/src/intel/isl/isl.c
@@ -197,14 +197,14 @@ isl_device_init(struct isl_device *dev,
assert(!(has_bit6_swizzling && info->gen >= 8));
dev->info = info;
- dev->use_separate_stencil = ISL_DEV_GEN(dev) >= 6;
+ dev->use_separate_stencil = ISL_GFX_VER(dev) >= 6;
dev->has_bit6_swizzling = has_bit6_swizzling;
/* The ISL_DEV macros may be defined in the CFLAGS, thus hardcoding some
* device properties at buildtime. Verify that the macros with the device
* properties chosen during runtime.
*/
- ISL_DEV_GEN_SANITIZE(dev);
+ ISL_GFX_VER_SANITIZE(dev);
ISL_DEV_USE_SEPARATE_STENCIL_SANITIZE(dev);
/* Did we break hiz or stencil? */
@@ -266,7 +266,7 @@ isl_device_init(struct isl_device *dev,
dev->ds.hiz_offset = 0;
}
- if (ISL_DEV_GEN(dev) >= 12) {
+ if (ISL_GFX_VER(dev) >= 12) {
dev->ds.size += GEN12_MI_LOAD_REGISTER_IMM_length * 4 * 2;
}
@@ -282,22 +282,22 @@ isl_device_init(struct isl_device *dev,
isl_sample_count_mask_t ATTRIBUTE_CONST
isl_device_get_sample_counts(struct isl_device *dev)
{
- if (ISL_DEV_GEN(dev) >= 9) {
+ if (ISL_GFX_VER(dev) >= 9) {
return ISL_SAMPLE_COUNT_1_BIT |
ISL_SAMPLE_COUNT_2_BIT |
ISL_SAMPLE_COUNT_4_BIT |
ISL_SAMPLE_COUNT_8_BIT |
ISL_SAMPLE_COUNT_16_BIT;
- } else if (ISL_DEV_GEN(dev) >= 8) {
+ } else if (ISL_GFX_VER(dev) >= 8) {
return ISL_SAMPLE_COUNT_1_BIT |
ISL_SAMPLE_COUNT_2_BIT |
ISL_SAMPLE_COUNT_4_BIT |
ISL_SAMPLE_COUNT_8_BIT;
- } else if (ISL_DEV_GEN(dev) >= 7) {
+ } else if (ISL_GFX_VER(dev) >= 7) {
return ISL_SAMPLE_COUNT_1_BIT |
ISL_SAMPLE_COUNT_4_BIT |
ISL_SAMPLE_COUNT_8_BIT;
- } else if (ISL_DEV_GEN(dev) >= 6) {
+ } else if (ISL_GFX_VER(dev) >= 6) {
return ISL_SAMPLE_COUNT_1_BIT |
ISL_SAMPLE_COUNT_4_BIT;
} else {
@@ -513,16 +513,16 @@ isl_surf_choose_tiling(const struct isl_device *dev,
/* CCS surfaces always use the CCS tiling */
if (info->usage & ISL_SURF_USAGE_CCS_BIT) {
assert(isl_format_get_layout(info->format)->txc == ISL_TXC_CCS);
- UNUSED bool ivb_ccs = ISL_DEV_GEN(dev) < 12 &&
+ UNUSED bool ivb_ccs = ISL_GFX_VER(dev) < 12 &&
tiling_flags == ISL_TILING_CCS_BIT;
- UNUSED bool tgl_ccs = ISL_DEV_GEN(dev) >= 12 &&
+ UNUSED bool tgl_ccs = ISL_GFX_VER(dev) >= 12 &&
tiling_flags == ISL_TILING_GEN12_CCS_BIT;
assert(ivb_ccs != tgl_ccs);
*tiling = isl_tiling_flag_to_enum(tiling_flags);
return true;
}
- if (ISL_DEV_GEN(dev) >= 6) {
+ if (ISL_GFX_VER(dev) >= 6) {
isl_gen6_filter_tiling(dev, info, &tiling_flags);
} else {
isl_gen4_filter_tiling(dev, info, &tiling_flags);
@@ -568,11 +568,11 @@ isl_choose_msaa_layout(const struct isl_device *dev,
enum isl_tiling tiling,
enum isl_msaa_layout *msaa_layout)
{
- if (ISL_DEV_GEN(dev) >= 8) {
+ if (ISL_GFX_VER(dev) >= 8) {
return isl_gen8_choose_msaa_layout(dev, info, tiling, msaa_layout);
- } else if (ISL_DEV_GEN(dev) >= 7) {
+ } else if (ISL_GFX_VER(dev) >= 7) {
return isl_gen7_choose_msaa_layout(dev, info, tiling, msaa_layout);
- } else if (ISL_DEV_GEN(dev) >= 6) {
+ } else if (ISL_GFX_VER(dev) >= 6) {
return isl_gen6_choose_msaa_layout(dev, info, tiling, msaa_layout);
} else {
return isl_gen4_choose_msaa_layout(dev, info, tiling, msaa_layout);
@@ -620,7 +620,7 @@ isl_choose_array_pitch_span(const struct isl_device *dev,
switch (dim_layout) {
case ISL_DIM_LAYOUT_GEN9_1D:
case ISL_DIM_LAYOUT_GEN4_2D:
- if (ISL_DEV_GEN(dev) >= 8) {
+ if (ISL_GFX_VER(dev) >= 8) {
/* QPitch becomes programmable in Broadwell. So choose the
* most compact QPitch possible in order to conserve memory.
*
@@ -641,7 +641,7 @@ isl_choose_array_pitch_span(const struct isl_device *dev,
* - Surface Type is SURFTYPE_CUBE
*/
return ISL_ARRAY_PITCH_SPAN_COMPACT;
- } else if (ISL_DEV_GEN(dev) >= 7) {
+ } else if (ISL_GFX_VER(dev) >= 7) {
/* Note that Ivybridge introduces
* RENDER_SURFACE_STATE.SurfaceArraySpacing, which provides the
* driver more control over the QPitch.
@@ -674,7 +674,7 @@ isl_choose_array_pitch_span(const struct isl_device *dev,
}
return ISL_ARRAY_PITCH_SPAN_FULL;
- } else if ((ISL_DEV_GEN(dev) == 5 || ISL_DEV_GEN(dev) == 6) &&
+ } else if ((ISL_GFX_VER(dev) == 5 || ISL_GFX_VER(dev) == 6) &&
ISL_DEV_USE_SEPARATE_STENCIL(dev) &&
isl_surf_usage_is_stencil(info->usage)) {
/* [ILK-SNB] Errata from the Sandy Bridge PRM >> Volume 4 Part 1:
@@ -686,7 +686,7 @@ isl_choose_array_pitch_span(const struct isl_device *dev,
assert(info->levels == 1);
return ISL_ARRAY_PITCH_SPAN_COMPACT;
} else {
- if ((ISL_DEV_GEN(dev) == 5 || ISL_DEV_GEN(dev) == 6) &&
+ if ((ISL_GFX_VER(dev) == 5 || ISL_GFX_VER(dev) == 6) &&
ISL_DEV_USE_SEPARATE_STENCIL(dev) &&
isl_surf_usage_is_stencil(info->usage)) {
/* [ILK-SNB] Errata from the Sandy Bridge PRM >> Volume 4 Part 1:
@@ -751,11 +751,11 @@ isl_choose_image_alignment_el(const struct isl_device *dev,
*image_align_el = isl_extent3d(4, 4, 1);
return;
} else if (info->format == ISL_FORMAT_HIZ) {
- assert(ISL_DEV_GEN(dev) >= 6);
- if (ISL_DEV_GEN(dev) == 6) {
+ assert(ISL_GFX_VER(dev) >= 6);
+ if (ISL_GFX_VER(dev) == 6) {
/* HiZ surfaces on Sandy Bridge are packed tightly. */
*image_align_el = isl_extent3d(1, 1, 1);
- } else if (ISL_DEV_GEN(dev) < 12) {
+ } else if (ISL_GFX_VER(dev) < 12) {
/* On gen7+, HiZ surfaces are always aligned to 16x8 pixels in the
* primary surface which works out to 2x2 HiZ elments.
*/
@@ -770,19 +770,19 @@ isl_choose_image_alignment_el(const struct isl_device *dev,
return;
}
- if (ISL_DEV_GEN(dev) >= 12) {
+ if (ISL_GFX_VER(dev) >= 12) {
isl_gen12_choose_image_alignment_el(dev, info, tiling, dim_layout,
msaa_layout, image_align_el);
- } else if (ISL_DEV_GEN(dev) >= 9) {
+ } else if (ISL_GFX_VER(dev) >= 9) {
isl_gen9_choose_image_alignment_el(dev, info, tiling, dim_layout,
msaa_layout, image_align_el);
- } else if (ISL_DEV_GEN(dev) >= 8) {
+ } else if (ISL_GFX_VER(dev) >= 8) {
isl_gen8_choose_image_alignment_el(dev, info, tiling, dim_layout,
msaa_layout, image_align_el);
- } else if (ISL_DEV_GEN(dev) >= 7) {
+ } else if (ISL_GFX_VER(dev) >= 7) {
isl_gen7_choose_image_alignment_el(dev, info, tiling, dim_layout,
msaa_layout, image_align_el);
- } else if (ISL_DEV_GEN(dev) >= 6) {
+ } else if (ISL_GFX_VER(dev) >= 6) {
isl_gen6_choose_image_alignment_el(dev, info, tiling, dim_layout,
msaa_layout, image_align_el);
} else {
@@ -798,11 +798,11 @@ isl_surf_choose_dim_layout(const struct isl_device *dev,
isl_surf_usage_flags_t usage)
{
/* Sandy bridge needs a special layout for HiZ and stencil. */
- if (ISL_DEV_GEN(dev) == 6 &&
+ if (ISL_GFX_VER(dev) == 6 &&
(tiling == ISL_TILING_W || tiling == ISL_TILING_HIZ))
return ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ;
- if (ISL_DEV_GEN(dev) >= 9) {
+ if (ISL_GFX_VER(dev) >= 9) {
switch (logical_dim) {
case ISL_SURF_DIM_1D:
/* From the Sky Lake PRM Vol. 5, "1D Surfaces":
@@ -838,7 +838,7 @@ isl_surf_choose_dim_layout(const struct isl_device *dev,
* however, the depth is equal to the number of faces (always 6) and
* is not reduced for each MIP.
*/
- if (ISL_DEV_GEN(dev) == 4 && (usage & ISL_SURF_USAGE_CUBE_BIT))
+ if (ISL_GFX_VER(dev) == 4 && (usage & ISL_SURF_USAGE_CUBE_BIT))
return ISL_DIM_LAYOUT_GEN4_3D;
return ISL_DIM_LAYOUT_GEN4_2D;
@@ -892,7 +892,7 @@ isl_calc_phys_level0_extent_sa(const struct isl_device *dev,
break;
case ISL_SURF_DIM_2D:
- if (ISL_DEV_GEN(dev) == 4 && (info->usage & ISL_SURF_USAGE_CUBE_BIT))
+ if (ISL_GFX_VER(dev) == 4 && (info->usage & ISL_SURF_USAGE_CUBE_BIT))
assert(dim_layout == ISL_DIM_LAYOUT_GEN4_3D);
else
assert(dim_layout == ISL_DIM_LAYOUT_GEN4_2D ||
@@ -962,7 +962,7 @@ isl_calc_phys_level0_extent_sa(const struct isl_device *dev,
unreachable("bad isl_dim_layout");
case ISL_DIM_LAYOUT_GEN4_2D:
- assert(ISL_DEV_GEN(dev) >= 9);
+ assert(ISL_GFX_VER(dev) >= 9);
*phys_level0_sa = (struct isl_extent4d) {
.w = info->width,
@@ -973,7 +973,7 @@ isl_calc_phys_level0_extent_sa(const struct isl_device *dev,
break;
case ISL_DIM_LAYOUT_GEN4_3D:
- assert(ISL_DEV_GEN(dev) < 9);
+ assert(ISL_GFX_VER(dev) < 9);
*phys_level0_sa = (struct isl_extent4d) {
.w = info->width,
.h = info->height,
@@ -1019,7 +1019,7 @@ isl_calc_array_pitch_el_rows_gen4_2d(
uint32_t h1_sa = isl_align_npot(H1_sa, image_align_sa->h);
uint32_t m;
- if (ISL_DEV_GEN(dev) >= 7) {
+ if (ISL_GFX_VER(dev) >= 7) {
/* The QPitch equation changed slightly in Ivybridge. */
m = 12;
} else {
@@ -1028,7 +1028,7 @@ isl_calc_array_pitch_el_rows_gen4_2d(
pitch_sa_rows = h0_sa + h1_sa + (m * image_align_sa->h);
- if (ISL_DEV_GEN(dev) == 6 && info->samples > 1 &&
+ if (ISL_GFX_VER(dev) == 6 && info->samples > 1 &&
(info->height % 4 == 1)) {
/* [SNB] Errata from the Sandy Bridge PRM >> Volume 4 Part 1:
* Graphics Core >> Section 7.18.3.7: Surface Arrays:
@@ -1051,7 +1051,7 @@ isl_calc_array_pitch_el_rows_gen4_2d(
assert(pitch_sa_rows % fmtl->bh == 0);
uint32_t pitch_el_rows = pitch_sa_rows / fmtl->bh;
- if (ISL_DEV_GEN(dev) >= 9 && ISL_DEV_GEN(dev) <= 11 &&
+ if (ISL_GFX_VER(dev) >= 9 && ISL_GFX_VER(dev) <= 11 &&
fmtl->txc == ISL_TXC_CCS) {
/*
* From the Sky Lake PRM Vol 7, "MCS Buffer for Render Target(s)" (p. 632):
@@ -1077,7 +1077,7 @@ isl_calc_array_pitch_el_rows_gen4_2d(
pitch_el_rows = isl_align(pitch_el_rows, 256 / 4);
}
- if (ISL_DEV_GEN(dev) >= 9 &&
+ if (ISL_GFX_VER(dev) >= 9 &&
info->dim == ISL_SURF_DIM_3D &&
tile_info->tiling != ISL_TILING_LINEAR) {
/* From the Skylake BSpec >> RENDER_SURFACE_STATE >> Surface QPitch:
@@ -1219,7 +1219,7 @@ isl_calc_phys_total_extent_el_gen4_3d(
* however, the depth is equal to the number of faces (always 6) and
* is not reduced for each MIP.
*/
- assert(ISL_DEV_GEN(dev) == 4);
+ assert(ISL_GFX_VER(dev) == 4);
assert(info->usage & ISL_SURF_USAGE_CUBE_BIT);
assert(phys_level0_sa->array_len == 6);
} else {
@@ -1423,7 +1423,7 @@ isl_calc_row_pitch_alignment(const struct isl_device *dev,
* isl_surf_get_ccs_surf() will check that the main surface alignment
* matches CCS expectations.
*/
- if (ISL_DEV_GEN(dev) >= 12 &&
+ if (ISL_GFX_VER(dev) >= 12 &&
isl_format_supports_ccs_e(dev->info, surf_info->format) &&
tile_info->tiling != ISL_TILING_X &&
!(surf_info->usage & ISL_SURF_USAGE_DISABLE_AUX_BIT) &&
@@ -1723,13 +1723,13 @@ isl_surf_init_s(const struct isl_device *dev,
* one thing we do know is that we haven't enable CCS on linear images
* yet so we can avoid the extra alignment there.
*/
- if (ISL_DEV_GEN(dev) >= 12 &&
+ if (ISL_GFX_VER(dev) >= 12 &&
!(info->usage & ISL_SURF_USAGE_DISABLE_AUX_BIT)) {
base_alignment_B = MAX(base_alignment_B, 64 * 1024);
}
}
- if (ISL_DEV_GEN(dev) < 9) {
+ if (ISL_GFX_VER(dev) < 9) {
/* From the Broadwell PRM Vol 5, Surface Layout:
*
* "In addition to restrictions on maximum height, width, and depth,
@@ -1740,7 +1740,7 @@ isl_surf_init_s(const struct isl_device *dev,
*/
if (size_B > (uint64_t) 1 << 31)
return false;
- } else if (ISL_DEV_GEN(dev) < 11) {
+ } else if (ISL_GFX_VER(dev) < 11) {
/* From the Skylake PRM Vol 5, Maximum Surface Size in Bytes:
* "In addition to restrictions on maximum height, width, and depth,
* surfaces are also restricted to a maximum size of 2^38 bytes.
@@ -1794,7 +1794,7 @@ isl_surf_get_hiz_surf(const struct isl_device *dev,
const struct isl_surf *surf,
struct isl_surf *hiz_surf)
{
- assert(ISL_DEV_GEN(dev) >= 5 && ISL_DEV_USE_SEPARATE_STENCIL(dev));
+ assert(ISL_GFX_VER(dev) >= 5 && ISL_DEV_USE_SEPARATE_STENCIL(dev));
if (!isl_surf_usage_is_depth(surf->usage))
return false;
@@ -1807,7 +1807,7 @@ isl_surf_get_hiz_surf(const struct isl_device *dev,
switch (surf->format) {
case ISL_FORMAT_R24_UNORM_X8_TYPELESS:
if (isl_surf_usage_is_depth_and_stencil(surf->usage)) {
- assert(ISL_DEV_GEN(dev) == 5);
+ assert(ISL_GFX_VER(dev) == 5);
unreachable("This should work, but is untested");
}
/* Fall through */
@@ -1815,7 +1815,7 @@ isl_surf_get_hiz_surf(const struct isl_device *dev,
case ISL_FORMAT_R32_FLOAT:
break;
case ISL_FORMAT_R32_FLOAT_X8X24_TYPELESS:
- if (ISL_DEV_GEN(dev) == 5) {
+ if (ISL_GFX_VER(dev) == 5) {
assert(isl_surf_usage_is_depth_and_stencil(surf->usage));
unreachable("This should work, but is untested");
}
@@ -1883,7 +1883,7 @@ isl_surf_get_hiz_surf(const struct isl_device *dev,
* without the need for additional HiZ formats with different block sizes
* on SKL+.
*/
- const unsigned samples = ISL_DEV_GEN(dev) >= 9 ? 1 : surf->samples;
+ const unsigned samples = ISL_GFX_VER(dev) >= 9 ? 1 : surf->samples;
return isl_surf_init(dev, hiz_surf,
.dim = surf->dim,
@@ -1927,7 +1927,7 @@ isl_surf_get_mcs_surf(const struct isl_device *dev,
* would require converting between CMS and UMS MSAA layouts on the fly,
* which is expensive.
*/
- if (ISL_DEV_GEN(dev) == 7 && isl_format_has_sint_channel(surf->format))
+ if (ISL_GFX_VER(dev) == 7 && isl_format_has_sint_channel(surf->format))
return false;
/* The "Auxiliary Surface Pitch" field in RENDER_SURFACE_STATE is only 9
@@ -1968,7 +1968,7 @@ isl_surf_supports_ccs(const struct isl_device *dev,
const struct isl_surf *surf)
{
/* CCS support does not exist prior to Gen7 */
- if (ISL_DEV_GEN(dev) <= 6)
+ if (ISL_GFX_VER(dev) <= 6)
return false;
if (surf->usage & ISL_SURF_USAGE_DISABLE_AUX_BIT)
@@ -2002,7 +2002,7 @@ isl_surf_supports_ccs(const struct isl_device *dev,
if (surf->tiling == ISL_TILING_LINEAR)
return false;
- if (ISL_DEV_GEN(dev) >= 12) {
+ if (ISL_GFX_VER(dev) >= 12) {
if (isl_surf_usage_is_stencil(surf->usage) && surf->samples > 1)
return false;
@@ -2038,7 +2038,7 @@ isl_surf_supports_ccs(const struct isl_device *dev,
if (surf->tiling != ISL_TILING_Y0)
return false;
} else {
- /* ISL_DEV_GEN(dev) < 12 */
+ /* ISL_GFX_VER(dev) < 12 */
if (surf->samples > 1)
return false;
@@ -2050,7 +2050,7 @@ isl_surf_supports_ccs(const struct isl_device *dev,
* work for 3D textures until gen9 where the layout of 3D textures
* changes to match 2D array textures.
*/
- if (ISL_DEV_GEN(dev) <= 8 && surf->dim != ISL_SURF_DIM_2D)
+ if (ISL_GFX_VER(dev) <= 8 && surf->dim != ISL_SURF_DIM_2D)
return false;
/* From the HSW PRM Volume 7: 3D-Media-GPGPU, page 652 (Color Clear of
@@ -2067,7 +2067,7 @@ isl_surf_supports_ccs(const struct isl_device *dev,
* follow the docs and don't allow CCS_D for arrayed or mip-mapped
* surfaces.
*/
- if (ISL_DEV_GEN(dev) <= 7 &&
+ if (ISL_GFX_VER(dev) <= 7 &&
(surf->levels > 1 || surf->logical_level0_px.array_len > 1))
return false;
@@ -2086,7 +2086,7 @@ isl_surf_supports_ccs(const struct isl_device *dev,
* - MCS and Lossless compression is supported for
* TiledY/TileYs/TileYf non-MSRTs only.
*/
- if (ISL_DEV_GEN(dev) >= 9 && !isl_tiling_is_any_y(surf->tiling))
+ if (ISL_GFX_VER(dev) >= 9 && !isl_tiling_is_any_y(surf->tiling))
return false;
}
@@ -2115,7 +2115,7 @@ isl_surf_get_ccs_surf(const struct isl_device *dev,
if (!isl_surf_supports_ccs(dev, surf))
return false;
- if (ISL_DEV_GEN(dev) >= 12) {
+ if (ISL_GFX_VER(dev) >= 12) {
enum isl_format ccs_format;
switch (isl_format_get_layout(surf->format)->bpb) {
case 8: ccs_format = ISL_FORMAT_GEN12_CCS_8BPP_Y0; break;
@@ -2149,7 +2149,7 @@ isl_surf_get_ccs_surf(const struct isl_device *dev,
return ok;
} else {
enum isl_format ccs_format;
- if (ISL_DEV_GEN(dev) >= 9) {
+ if (ISL_GFX_VER(dev) >= 9) {
switch (isl_format_get_layout(surf->format)->bpb) {
case 32: ccs_format = ISL_FORMAT_GEN9_CCS_32BPP; break;
case 64: ccs_format = ISL_FORMAT_GEN9_CCS_64BPP; break;
@@ -2191,7 +2191,7 @@ isl_surf_get_ccs_surf(const struct isl_device *dev,
}
#define isl_genX_call(dev, func, ...) \
- switch (ISL_DEV_GENX10(dev)) { \
+ switch (ISL_GFX_VERX10(dev)) { \
case 40: \
isl_gen4_##func(__VA_ARGS__); \
break; \
@@ -2767,23 +2767,23 @@ isl_surf_get_depth_format(const struct isl_device *dev,
assert(surf->usage & ISL_SURF_USAGE_DEPTH_BIT);
if (has_stencil)
- assert(ISL_DEV_GEN(dev) < 7);
+ assert(ISL_GFX_VER(dev) < 7);
switch (surf->format) {
default:
unreachable("bad isl depth format");
case ISL_FORMAT_R32_FLOAT_X8X24_TYPELESS:
- assert(ISL_DEV_GEN(dev) < 7);
+ assert(ISL_GFX_VER(dev) < 7);
return 0; /* D32_FLOAT_S8X24_UINT */
case ISL_FORMAT_R32_FLOAT:
assert(!has_stencil);
return 1; /* D32_FLOAT */
case ISL_FORMAT_R24_UNORM_X8_TYPELESS:
if (has_stencil) {
- assert(ISL_DEV_GEN(dev) < 7);
+ assert(ISL_GFX_VER(dev) < 7);
return 2; /* D24_UNORM_S8_UINT */
} else {
- assert(ISL_DEV_GEN(dev) >= 5);
+ assert(ISL_GFX_VER(dev) >= 5);
return 3; /* D24_UNORM_X8_UINT */
}
case ISL_FORMAT_R16_UNORM:
diff --git a/src/intel/isl/isl.h b/src/intel/isl/isl.h
index 296fa36defd..0f9e21729ce 100644
--- a/src/intel/isl/isl.h
+++ b/src/intel/isl/isl.h
@@ -53,20 +53,20 @@ extern "C" {
struct gen_device_info;
struct brw_image_param;
-#ifndef ISL_DEV_GEN
+#ifndef ISL_GFX_VER
/**
* @brief Get the hardware generation of isl_device.
*
* You can define this as a compile-time constant in the CFLAGS. For example,
- * `gcc -DISL_DEV_GEN(dev)=9 ...`.
+ * `gcc -DISL_GFX_VER(dev)=9 ...`.
*/
-#define ISL_DEV_GEN(__dev) ((__dev)->info->gen)
-#define ISL_DEV_GENX10(__dev) ((__dev)->info->genx10)
-#define ISL_DEV_GEN_SANITIZE(__dev)
+#define ISL_GFX_VER(__dev) ((__dev)->info->gen)
+#define ISL_GFX_VERX10(__dev) ((__dev)->info->genx10)
+#define ISL_GFX_VER_SANITIZE(__dev)
#else
-#define ISL_DEV_GEN_SANITIZE(__dev) \
- (assert(ISL_DEV_GEN(__dev) == (__dev)->info->gen) && \
- ISL_DEV_GENX10(__dev) == (__dev)->info->genx10))
+#define ISL_GFX_VER_SANITIZE(__dev) \
+ (assert(ISL_GFX_VER(__dev) == (__dev)->info->gen) && \
+ ISL_GFX_VERX10(__dev) == (__dev)->info->genx10))
#endif
#ifndef ISL_DEV_IS_G4X
@@ -78,7 +78,7 @@ struct brw_image_param;
* @brief Get the hardware generation of isl_device.
*
* You can define this as a compile-time constant in the CFLAGS. For example,
- * `gcc -DISL_DEV_GEN(dev)=9 ...`.
+ * `gcc -DISL_GFX_VER(dev)=9 ...`.
*/
#define ISL_DEV_IS_HASWELL(__dev) ((__dev)->info->is_haswell)
#endif
diff --git a/src/intel/isl/isl_gen4.c b/src/intel/isl/isl_gen4.c
index a212d0ee0af..493870c7ccc 100644
--- a/src/intel/isl/isl_gen4.c
+++ b/src/intel/isl/isl_gen4.c
@@ -58,7 +58,7 @@ isl_gen4_filter_tiling(const struct isl_device *dev,
*
* In testing, the linear configuration doesn't seem to work on gen4.
*/
- *flags &= (ISL_DEV_GEN(dev) == 4 && !ISL_DEV_IS_G4X(dev)) ?
+ *flags &= (ISL_GFX_VER(dev) == 4 && !ISL_DEV_IS_G4X(dev)) ?
ISL_TILING_Y0_BIT : (ISL_TILING_Y0_BIT | ISL_TILING_LINEAR_BIT);
}
diff --git a/src/intel/isl/isl_gen6.c b/src/intel/isl/isl_gen6.c
index 51f2100ac83..b3a39f33364 100644
--- a/src/intel/isl/isl_gen6.c
+++ b/src/intel/isl/isl_gen6.c
@@ -30,7 +30,7 @@ isl_gen6_choose_msaa_layout(const struct isl_device *dev,
enum isl_tiling tiling,
enum isl_msaa_layout *msaa_layout)
{
- assert(ISL_DEV_GEN(dev) == 6);
+ assert(ISL_GFX_VER(dev) == 6);
assert(info->samples >= 1);
if (info->samples == 1) {
diff --git a/src/intel/isl/isl_gen7.c b/src/intel/isl/isl_gen7.c
index fa245667968..1a2d345bea6 100644
--- a/src/intel/isl/isl_gen7.c
+++ b/src/intel/isl/isl_gen7.c
@@ -28,7 +28,7 @@ static bool
gen7_format_needs_valign2(const struct isl_device *dev,
enum isl_format format)
{
- assert(ISL_DEV_GEN(dev) == 7);
+ assert(ISL_GFX_VER(dev) == 7);
/* From the Ivybridge PRM (2012-05-31), Volume 4, Part 1, Section 2.12.1,
* RENDER_SURFACE_STATE Surface Vertical Alignment:
@@ -54,7 +54,7 @@ isl_gen7_choose_msaa_layout(const struct isl_device *dev,
bool require_array = false;
bool require_interleaved = false;
- assert(ISL_DEV_GEN(dev) == 7);
+ assert(ISL_GFX_VER(dev) == 7);
assert(info->samples >= 1);
if (info->samples == 1) {
@@ -197,7 +197,7 @@ isl_gen6_filter_tiling(const struct isl_device *dev,
assert(ISL_DEV_USE_SEPARATE_STENCIL(dev));
/* Clear flags unsupported on this hardware */
- if (ISL_DEV_GEN(dev) < 9) {
+ if (ISL_GFX_VER(dev) < 9) {
*flags &= ~ISL_TILING_Yf_BIT;
*flags &= ~ISL_TILING_Ys_BIT;
}
@@ -214,7 +214,7 @@ isl_gen6_filter_tiling(const struct isl_device *dev,
}
if (isl_surf_usage_is_stencil(info->usage)) {
- if (ISL_DEV_GEN(dev) >= 12) {
+ if (ISL_GFX_VER(dev) >= 12) {
/* Stencil requires Y. */
*flags &= ISL_TILING_ANY_Y_MASK;
} else {
@@ -251,10 +251,10 @@ isl_gen6_filter_tiling(const struct isl_device *dev,
}
if (info->usage & ISL_SURF_USAGE_DISPLAY_BIT) {
- if (ISL_DEV_GEN(dev) >= 12) {
+ if (ISL_GFX_VER(dev) >= 12) {
*flags &= (ISL_TILING_LINEAR_BIT | ISL_TILING_X_BIT |
ISL_TILING_Y0_BIT);
- } else if (ISL_DEV_GEN(dev) >= 9) {
+ } else if (ISL_GFX_VER(dev) >= 9) {
/* Note we let Yf even though it was cleared above. This is just for
* completeness.
*/
@@ -285,7 +285,7 @@ isl_gen6_filter_tiling(const struct isl_device *dev,
}
/* workaround */
- if (ISL_DEV_GEN(dev) == 7 &&
+ if (ISL_GFX_VER(dev) == 7 &&
gen7_format_needs_valign2(dev, info->format) &&
(info->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT) &&
info->samples == 1) {
@@ -305,7 +305,7 @@ isl_gen6_filter_tiling(const struct isl_device *dev,
*
* This is necessary all the way back to 965, but is permitted on Gen7+.
*/
- if (ISL_DEV_GEN(dev) < 7 && isl_format_get_layout(info->format)->bpb >= 128)
+ if (ISL_GFX_VER(dev) < 7 && isl_format_get_layout(info->format)->bpb >= 128)
*flags &= ~ISL_TILING_Y0_BIT;
/* From the BDW and SKL PRMs, Volume 2d,
@@ -326,7 +326,7 @@ isl_gen6_filter_tiling(const struct isl_device *dev,
*/
if (info->width > 16382 && info->samples == 1 &&
info->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT &&
- (ISL_DEV_GEN(dev) == 8 ||
+ (ISL_GFX_VER(dev) == 8 ||
(dev->info->is_skylake && dev->info->gt != 4))) {
*flags &= ISL_TILING_LINEAR_BIT;
}
@@ -340,7 +340,7 @@ isl_gen7_choose_image_alignment_el(const struct isl_device *dev,
enum isl_msaa_layout msaa_layout,
struct isl_extent3d *image_align_el)
{
- assert(ISL_DEV_GEN(dev) == 7);
+ assert(ISL_GFX_VER(dev) == 7);
/* Handled by isl_choose_image_alignment_el */
assert(info->format != ISL_FORMAT_HIZ);
diff --git a/src/intel/isl/isl_gen8.c b/src/intel/isl/isl_gen8.c
index fe6166fc4ea..1b93e984650 100644
--- a/src/intel/isl/isl_gen8.c
+++ b/src/intel/isl/isl_gen8.c
@@ -173,7 +173,7 @@ isl_gen8_choose_image_alignment_el(const struct isl_device *dev,
halign = 16;
}
- if (ISL_DEV_GEN(dev) >= 11 && isl_tiling_is_any_y(tiling) &&
+ if (ISL_GFX_VER(dev) >= 11 && isl_tiling_is_any_y(tiling) &&
fmtl->bpb == 32 && info->samples == 1) {
/* GEN_BUG_1406667188: Pixel Corruption in subspan combining (8x4
* combining) scenarios if halign=4.
diff --git a/src/intel/isl/isl_storage_image.c b/src/intel/isl/isl_storage_image.c
index f8bb5275358..5e3adb97d6c 100644
--- a/src/intel/isl/isl_storage_image.c
+++ b/src/intel/isl/isl_storage_image.c
@@ -253,7 +253,7 @@ isl_surf_fill_image_param(const struct isl_device *dev,
const struct isl_extent3d image_align_sa =
isl_surf_get_image_alignment_sa(surf);
- if (ISL_DEV_GEN(dev) < 9 && surf->dim == ISL_SURF_DIM_3D) {
+ if (ISL_GFX_VER(dev) < 9 && surf->dim == ISL_SURF_DIM_3D) {
param->stride[2] = isl_align_npot(param->size[0], image_align_sa.w);
param->stride[3] = isl_align_npot(param->size[1], image_align_sa.h);
} else {
@@ -307,7 +307,7 @@ isl_surf_fill_image_param(const struct isl_device *dev,
* brw_fs_surface_builder.cpp) handles this as a sort of tiling with
* modulus equal to the LOD.
*/
- param->tiling[2] = (ISL_DEV_GEN(dev) < 9 && surf->dim == ISL_SURF_DIM_3D ?
+ param->tiling[2] = (ISL_GFX_VER(dev) < 9 && surf->dim == ISL_SURF_DIM_3D ?
view->base_level : 0);
}
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