Mesa (master): intel: Rename GEN:BUG:### to Wa_###
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gitlab-mirror at kemper.freedesktop.org
Fri Apr 2 18:41:13 UTC 2021
Module: Mesa
Branch: master
Commit: f96c3b8b63ab7185168dd10d56779583c8f516ce
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f96c3b8b63ab7185168dd10d56779583c8f516ce
Author: Anuj Phogat <anuj.phogat at gmail.com>
Date: Mon Mar 29 17:15:41 2021 -0700
intel: Rename GEN:BUG:### to Wa_###
Commands used to do the changes:
export SEARCH_PATH="src/intel src/gallium/drivers/iris src/mesa/drivers/dri/i965"
grep -E "GEN:BUG:" -rIl $SEARCH_PATH | xargs sed -ie "s/GEN\(:BUG:\)/Wa_/g"
Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9936>
---
src/gallium/drivers/iris/iris_state.c | 24 +++++++++++-----------
src/intel/blorp/blorp_genX_exec.h | 4 ++--
src/intel/compiler/brw_eu_validate.c | 2 +-
src/intel/compiler/brw_fs.cpp | 6 +++---
src/intel/compiler/brw_fs_generator.cpp | 2 +-
src/intel/compiler/brw_fs_scoreboard.cpp | 6 +++---
.../brw_nir_clamp_image_1d_2d_array_sizes.c | 2 +-
src/intel/isl/isl.c | 4 ++--
src/intel/isl/isl_emit_depth_stencil.c | 4 ++--
src/intel/isl/isl_surface_state.c | 2 +-
src/intel/vulkan/genX_cmd_buffer.c | 18 ++++++++--------
src/intel/vulkan/genX_pipeline.c | 2 +-
src/intel/vulkan/gfx7_cmd_buffer.c | 2 +-
src/intel/vulkan/gfx8_cmd_buffer.c | 2 +-
src/mesa/drivers/dri/i965/genX_state_upload.c | 2 +-
15 files changed, 41 insertions(+), 41 deletions(-)
diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c
index 543e70fa68e..6a53e8834a3 100644
--- a/src/gallium/drivers/iris/iris_state.c
+++ b/src/gallium/drivers/iris/iris_state.c
@@ -410,7 +410,7 @@ flush_before_state_base_change(struct iris_batch *batch)
PIPE_CONTROL_RENDER_TARGET_FLUSH |
PIPE_CONTROL_DEPTH_CACHE_FLUSH |
PIPE_CONTROL_DATA_CACHE_FLUSH |
- /* GEN:BUG:1606662791:
+ /* Wa_1606662791:
*
* Software must program PIPE_CONTROL command
* with "HDC Pipeline Flush" prior to
@@ -1091,7 +1091,7 @@ iris_init_compute_context(struct iris_batch *batch)
iris_batch_sync_region_start(batch);
- /* GEN:BUG:1607854226:
+ /* Wa_1607854226:
*
* Start with pipeline in 3D mode to set the STATE_BASE_ADDRESS.
*/
@@ -4383,7 +4383,7 @@ iris_store_tcs_state(const struct gen_device_info *devinfo,
INIT_THREAD_DISPATCH_FIELDS(hs, Vertex, MESA_SHADER_TESS_CTRL);
#if GFX_VER >= 12
- /* GEN:BUG:1604578095:
+ /* Wa_1604578095:
*
* Hang occurs when the number of max threads is less than 2 times
* the number of instance count. The number of max threads must be
@@ -5312,7 +5312,7 @@ iris_update_surface_base_address(struct iris_batch *batch,
flush_before_state_base_change(batch);
#if GFX_VER == 12
- /* GEN:BUG:1607854226:
+ /* Wa_1607854226:
*
* Workaround the non pipelined state not applying in MEDIA/GPGPU pipeline
* mode by putting the pipeline temporarily in 3D mode..
@@ -5340,7 +5340,7 @@ iris_update_surface_base_address(struct iris_batch *batch,
}
#if GFX_VER == 12
- /* GEN:BUG:1607854226:
+ /* Wa_1607854226:
*
* Put the pipeline back into compute mode.
*/
@@ -5747,7 +5747,7 @@ iris_upload_dirty_render_state(struct iris_context *ice,
}
}
- /* GEN:BUG:1604061319
+ /* Wa_1604061319
*
* 3DSTATE_CONSTANT_* needs to be programmed before BTP_*
*
@@ -6190,7 +6190,7 @@ iris_upload_dirty_render_state(struct iris_context *ice,
}
if (dirty & IRIS_DIRTY_SCISSOR_RECT) {
- /* GEN:BUG:1409725701:
+ /* Wa_1409725701:
* "The viewport-specific state used by the SF unit (SCISSOR_RECT) is
* stored as an array of up to 16 elements. The location of first
* element of the array, as specified by Pointer to SCISSOR_RECT,
@@ -6219,7 +6219,7 @@ iris_upload_dirty_render_state(struct iris_context *ice,
uint32_t cso_z_size = batch->screen->isl_dev.ds.size - clear_length;;
#if GFX_VER == 12
- /* GEN:BUG:14010455700
+ /* Wa_14010455700
*
* ISL will change some CHICKEN registers depending on the depth surface
* format, along with emitting the depth and stencil packets. In that
@@ -6234,7 +6234,7 @@ iris_upload_dirty_render_state(struct iris_context *ice,
iris_batch_emit(batch, cso_z->packets, cso_z_size);
if (GFX_VER >= 12) {
- /* GEN:BUG:1408224581
+ /* Wa_1408224581
*
* Workaround: Gfx12LP Astep only An additional pipe control with
* post-sync = store dword operation would be required.( w/a is to
@@ -7401,7 +7401,7 @@ iris_emit_raw_pipe_control(struct iris_batch *batch,
0, NULL, 0, 0);
}
- /* GEN:BUG:1409226450, Wait for EU to be idle before pipe control which
+ /* Wa_1409226450, Wait for EU to be idle before pipe control which
* invalidates the instruction cache
*/
if (GFX_VER == 12 && (flags & PIPE_CONTROL_INSTRUCTION_INVALIDATE)) {
@@ -7424,7 +7424,7 @@ iris_emit_raw_pipe_control(struct iris_batch *batch,
*
* The same text exists a few rows below for Post Sync Op.
*
- * On Gfx12 this is GEN:BUG:1607156449.
+ * On Gfx12 this is Wa_1607156449.
*/
iris_emit_raw_pipe_control(batch,
"workaround: CS stall before gpgpu post-sync",
@@ -7706,7 +7706,7 @@ iris_emit_raw_pipe_control(struct iris_batch *batch,
}
if (GFX_VER >= 12 && (flags & PIPE_CONTROL_DEPTH_CACHE_FLUSH)) {
- /* GEN:BUG:1409600907:
+ /* Wa_1409600907:
*
* "PIPE_CONTROL with Depth Stall Enable bit must be set
* with any PIPE_CONTROL with Depth Flush Enable bit set.
diff --git a/src/intel/blorp/blorp_genX_exec.h b/src/intel/blorp/blorp_genX_exec.h
index 49aef172e6b..f4ed2e0cc07 100644
--- a/src/intel/blorp/blorp_genX_exec.h
+++ b/src/intel/blorp/blorp_genX_exec.h
@@ -1698,7 +1698,7 @@ blorp_emit_depth_stencil_config(struct blorp_batch *batch,
isl_emit_depth_stencil_hiz_s(isl_dev, dw, &info);
#if GFX_VER >= 12
- /* GEN:BUG:1408224581
+ /* Wa_1408224581
*
* Workaround: Gfx12LP Astep only An additional pipe control with
* post-sync = store dword operation would be required.( w/a is to
@@ -1872,7 +1872,7 @@ blorp_update_clear_color(UNUSED struct blorp_batch *batch,
}
#elif GFX_VER >= 9
- /* According to GEN:BUG:2201730850, in the Clear Color Programming Note
+ /* According to Wa_2201730850, in the Clear Color Programming Note
* under the Red channel, "Software shall write the converted Depth
* Clear to this dword." The only depth formats listed under the red
* channel are IEEE_FP and UNORM24_X8. These two requirements are
diff --git a/src/intel/compiler/brw_eu_validate.c b/src/intel/compiler/brw_eu_validate.c
index e9dac16d208..17071e8e94c 100644
--- a/src/intel/compiler/brw_eu_validate.c
+++ b/src/intel/compiler/brw_eu_validate.c
@@ -1912,7 +1912,7 @@ instruction_restrictions(const struct gen_device_info *devinfo,
{
struct string error_msg = { .str = NULL, .len = 0 };
- /* From GEN:BUG:1604601757:
+ /* From Wa_1604601757:
*
* "When multiplying a DW and any lower precision integer, source modifier
* is not supported."
diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp
index f5353c8ee29..cb1d33ecfdb 100644
--- a/src/intel/compiler/brw_fs.cpp
+++ b/src/intel/compiler/brw_fs.cpp
@@ -439,7 +439,7 @@ fs_inst::can_do_source_mods(const struct gen_device_info *devinfo) const
if (is_send_from_grf())
return false;
- /* From GEN:BUG:1604601757:
+ /* From Wa_1604601757:
*
* "When multiplying a DW and any lower precision integer, source modifier
* is not supported."
@@ -4024,7 +4024,7 @@ fs_visitor::lower_mul_dword_inst(fs_inst *inst, bblock_t *block)
high.offset = inst->dst.offset % REG_SIZE;
if (devinfo->ver >= 7) {
- /* From GEN:BUG:1604601757:
+ /* From Wa_1604601757:
*
* "When multiplying a DW and any lower precision integer, source modifier
* is not supported."
@@ -8076,7 +8076,7 @@ find_halt_control_flow_region_start(const fs_visitor *v)
}
/**
- * Work around the Gfx12 hardware bug filed as GEN:BUG:1407528679. EU fusion
+ * Work around the Gfx12 hardware bug filed as Wa_1407528679. EU fusion
* can cause a BB to be executed with all channels disabled, which will lead
* to the execution of any NoMask instructions in it, even though any
* execution-masked instructions will be correctly shot down. This may break
diff --git a/src/intel/compiler/brw_fs_generator.cpp b/src/intel/compiler/brw_fs_generator.cpp
index f25372bcbfa..aef20e440af 100644
--- a/src/intel/compiler/brw_fs_generator.cpp
+++ b/src/intel/compiler/brw_fs_generator.cpp
@@ -1943,7 +1943,7 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width,
nop_count++;
}
- /* GEN:BUG:14010017096:
+ /* Wa_14010017096:
*
* Clear accumulator register before end of thread.
*/
diff --git a/src/intel/compiler/brw_fs_scoreboard.cpp b/src/intel/compiler/brw_fs_scoreboard.cpp
index 70f48ec2110..9f7b78b78cc 100644
--- a/src/intel/compiler/brw_fs_scoreboard.cpp
+++ b/src/intel/compiler/brw_fs_scoreboard.cpp
@@ -335,7 +335,7 @@ namespace {
* Whether the dependency could be run with execution masking disabled,
* which might lead to the unwanted execution of the generating
* instruction in cases where a BB is executed with all channels
- * disabled due to hardware bug GEN:BUG:1407528679.
+ * disabled due to hardware bug Wa_1407528679.
*/
bool exec_all;
@@ -1024,7 +1024,7 @@ namespace {
* possible, except in cases where the current instruction
* isn't marked NoMask but the dependency is, since that
* might lead to data coherency issues due to
- * GEN:BUG:1407528679.
+ * Wa_1407528679.
*/
swsb.sbid = dep.id;
swsb.mode = dep.unordered;
@@ -1051,7 +1051,7 @@ namespace {
/* If the current instruction is not marked NoMask but an
* ordered dependency is, perform the synchronization as a
* separate NoMask SYNC instruction in order to avoid data
- * coherency issues due to GEN:BUG:1407528679. The similar
+ * coherency issues due to Wa_1407528679. The similar
* scenario with unordered dependencies should have been
* handled above.
*/
diff --git a/src/intel/compiler/brw_nir_clamp_image_1d_2d_array_sizes.c b/src/intel/compiler/brw_nir_clamp_image_1d_2d_array_sizes.c
index 22b682e4987..0daae1d6e7a 100644
--- a/src/intel/compiler/brw_nir_clamp_image_1d_2d_array_sizes.c
+++ b/src/intel/compiler/brw_nir_clamp_image_1d_2d_array_sizes.c
@@ -25,7 +25,7 @@
#include "brw_nir.h"
/**
- * GEN:BUG:1806565034:
+ * Wa_1806565034:
*
* Gfx12+ allows to set RENDER_SURFACE_STATE::SurfaceArray to 1 only if
* array_len > 1. Setting RENDER_SURFACE_STATE::SurfaceArray to 0 results in
diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
index 040ddf0cf60..76a80eb1338 100644
--- a/src/intel/isl/isl.c
+++ b/src/intel/isl/isl.c
@@ -2012,7 +2012,7 @@ isl_surf_supports_ccs(const struct isl_device *dev,
if (surf->row_pitch_B % 512 != 0)
return false;
- /* According to GEN:BUG:1406738321, 3D textures need a blit to a new
+ /* According to Wa_1406738321, 3D textures need a blit to a new
* surface in order to perform a resolve. For now, just disable CCS.
*/
if (surf->dim == ISL_SURF_DIM_3D) {
@@ -2021,7 +2021,7 @@ isl_surf_supports_ccs(const struct isl_device *dev,
return false;
}
- /* GEN:BUG:1207137018
+ /* Wa_1207137018
*
* TODO: implement following workaround currently covered by the
* restriction above. If following conditions are met:
diff --git a/src/intel/isl/isl_emit_depth_stencil.c b/src/intel/isl/isl_emit_depth_stencil.c
index 2aa62e3d179..55ff5686c8e 100644
--- a/src/intel/isl/isl_emit_depth_stencil.c
+++ b/src/intel/isl/isl_emit_depth_stencil.c
@@ -305,7 +305,7 @@ isl_genX(emit_depth_stencil_hiz_s)(const struct isl_device *dev, void *batch,
dw += GENX(3DSTATE_HIER_DEPTH_BUFFER_length);
#if GFX_VER == 12
- /* GEN:BUG:14010455700
+ /* Wa_14010455700
*
* To avoid sporadic corruptions “Set 0x7010[9] when Depth Buffer Surface
* Format is D16_UNORM , surface type is not NULL & 1X_MSAA”.
@@ -328,7 +328,7 @@ isl_genX(emit_depth_stencil_hiz_s)(const struct isl_device *dev, void *batch,
GENX(MI_LOAD_REGISTER_IMM_pack)(NULL, dw, &lri);
dw += GENX(MI_LOAD_REGISTER_IMM_length);
- /* GEN:BUG:1806527549
+ /* Wa_1806527549
*
* Set HIZ_CHICKEN (7018h) bit 13 = 1 when depth buffer is D16_UNORM.
*/
diff --git a/src/intel/isl/isl_surface_state.c b/src/intel/isl/isl_surface_state.c
index bb801784ee7..0576d5179d6 100644
--- a/src/intel/isl/isl_surface_state.c
+++ b/src/intel/isl/isl_surface_state.c
@@ -435,7 +435,7 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state,
}
#if GFX_VER >= 12
- /* GEN:BUG:1806565034: Only set SurfaceArray if arrayed surface is > 1. */
+ /* Wa_1806565034: Only set SurfaceArray if arrayed surface is > 1. */
s.SurfaceArray = info->surf->dim != ISL_SURF_DIM_3D &&
info->view->array_len > 1;
#elif GFX_VER >= 7
diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c
index 4313aa2878c..c8fd7cb18f3 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -75,7 +75,7 @@ genX(cmd_buffer_emit_state_base_address)(struct anv_cmd_buffer *cmd_buffer)
pc.TileCacheFlushEnable = true;
#endif
#if GFX_VER == 12
- /* GEN:BUG:1606662791:
+ /* Wa_1606662791:
*
* Software must program PIPE_CONTROL command with "HDC Pipeline
* Flush" prior to programming of the below two non-pipeline state :
@@ -88,7 +88,7 @@ genX(cmd_buffer_emit_state_base_address)(struct anv_cmd_buffer *cmd_buffer)
}
#if GFX_VER == 12
- /* GEN:BUG:1607854226:
+ /* Wa_1607854226:
*
* Workaround the non pipelined state not applying in MEDIA/GPGPU pipeline
* mode by putting the pipeline temporarily in 3D mode.
@@ -185,7 +185,7 @@ genX(cmd_buffer_emit_state_base_address)(struct anv_cmd_buffer *cmd_buffer)
}
#if GFX_VER == 12
- /* GEN:BUG:1607854226:
+ /* Wa_1607854226:
*
* Put the pipeline back into its current mode.
*/
@@ -2022,7 +2022,7 @@ genX(cmd_buffer_apply_pipe_flushes)(struct anv_cmd_buffer *cmd_buffer)
bits |= ANV_PIPE_TILE_CACHE_FLUSH_BIT;
}
- /* GEN:BUG:1409226450, Wait for EU to be idle before pipe control which
+ /* Wa_1409226450, Wait for EU to be idle before pipe control which
* invalidates the instruction cache
*/
if (GFX_VER == 12 && (bits & ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT))
@@ -2049,7 +2049,7 @@ genX(cmd_buffer_apply_pipe_flushes)(struct anv_cmd_buffer *cmd_buffer)
*
* The same text exists a few rows below for Post Sync Op.
*
- * On Gfx12 this is GEN:BUG:1607156449.
+ * On Gfx12 this is Wa_1607156449.
*/
if (bits & ANV_PIPE_POST_SYNC_BIT) {
if ((GFX_VER == 9 || (GFX_VER == 12 && devinfo->revision == 0 /* A0 */)) &&
@@ -2069,7 +2069,7 @@ genX(cmd_buffer_apply_pipe_flushes)(struct anv_cmd_buffer *cmd_buffer)
pipe.RenderTargetCacheFlushEnable =
bits & ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT;
- /* GEN:BUG:1409600907: "PIPE_CONTROL with Depth Stall Enable bit must
+ /* Wa_1409600907: "PIPE_CONTROL with Depth Stall Enable bit must
* be set with any PIPE_CONTROL with Depth Flush Enable bit set.
*/
#if GFX_VER >= 12
@@ -4763,7 +4763,7 @@ genX(flush_pipeline_select)(struct anv_cmd_buffer *cmd_buffer,
#if GFX_VER >= 12
pc.TileCacheFlushEnable = true;
- /* GEN:BUG:1409600907: "PIPE_CONTROL with Depth Stall Enable bit must be
+ /* Wa_1409600907: "PIPE_CONTROL with Depth Stall Enable bit must be
* set with any PIPE_CONTROL with Depth Flush Enable bit set.
*/
pc.DepthStallEnable = true;
@@ -5142,7 +5142,7 @@ cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer *cmd_buffer)
cmd_buffer->state.pending_pipe_bits |= ANV_PIPE_POST_SYNC_BIT;
genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer);
- /* GEN:BUG:1408224581
+ /* Wa_1408224581
*
* Workaround: Gfx12LP Astep only An additional pipe control with
* post-sync = store dword operation would be required.( w/a is to
@@ -5573,7 +5573,7 @@ cmd_buffer_begin_subpass(struct anv_cmd_buffer *cmd_buffer,
#endif
#if GFX_VER == 12
- /* GEN:BUG:14010455700
+ /* Wa_14010455700
*
* ISL will change some CHICKEN registers depending on the depth surface
* format, along with emitting the depth and stencil packets. In that case,
diff --git a/src/intel/vulkan/genX_pipeline.c b/src/intel/vulkan/genX_pipeline.c
index 3a87d772ec7..7f337ac564e 100644
--- a/src/intel/vulkan/genX_pipeline.c
+++ b/src/intel/vulkan/genX_pipeline.c
@@ -1697,7 +1697,7 @@ emit_3dstate_hs_te_ds(struct anv_graphics_pipeline *pipeline,
hs.BindingTableEntryCount = tcs_bin->bind_map.surface_count;
#if GFX_VER >= 12
- /* GEN:BUG:1604578095:
+ /* Wa_1604578095:
*
* Hang occurs when the number of max threads is less than 2 times
* the number of instance count. The number of max threads must be
diff --git a/src/intel/vulkan/gfx7_cmd_buffer.c b/src/intel/vulkan/gfx7_cmd_buffer.c
index 06a4965014c..e5ecfb671f9 100644
--- a/src/intel/vulkan/gfx7_cmd_buffer.c
+++ b/src/intel/vulkan/gfx7_cmd_buffer.c
@@ -52,7 +52,7 @@ gfx7_cmd_buffer_emit_scissor(struct anv_cmd_buffer *cmd_buffer)
uint32_t count = cmd_buffer->state.gfx.dynamic.scissor.count;
const VkRect2D *scissors = cmd_buffer->state.gfx.dynamic.scissor.scissors;
- /* GEN:BUG:1409725701:
+ /* Wa_1409725701:
* "The viewport-specific state used by the SF unit (SCISSOR_RECT) is
* stored as an array of up to 16 elements. The location of first
* element of the array, as specified by Pointer to SCISSOR_RECT, should
diff --git a/src/intel/vulkan/gfx8_cmd_buffer.c b/src/intel/vulkan/gfx8_cmd_buffer.c
index cd5eb1a8ddc..2631247ba28 100644
--- a/src/intel/vulkan/gfx8_cmd_buffer.c
+++ b/src/intel/vulkan/gfx8_cmd_buffer.c
@@ -151,7 +151,7 @@ genX(cmd_buffer_enable_pma_fix)(struct anv_cmd_buffer *cmd_buffer, bool enable)
#if GFX_VER >= 12
pc.TileCacheFlushEnable = true;
- /* GEN:BUG:1409600907: "PIPE_CONTROL with Depth Stall Enable bit must
+ /* Wa_1409600907: "PIPE_CONTROL with Depth Stall Enable bit must
* be set with any PIPE_CONTROL with Depth Flush Enable bit set.
*/
pc.DepthStallEnable = true;
diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c b/src/mesa/drivers/dri/i965/genX_state_upload.c
index 3ded268e1a6..2ff9cb02cda 100644
--- a/src/mesa/drivers/dri/i965/genX_state_upload.c
+++ b/src/mesa/drivers/dri/i965/genX_state_upload.c
@@ -2364,7 +2364,7 @@ genX(upload_scissor_state)(struct brw_context *brw)
/* BRW_NEW_VIEWPORT_COUNT */
const unsigned viewport_count = brw->clip.viewport_count;
- /* GEN:BUG:1409725701:
+ /* Wa_1409725701:
* "The viewport-specific state used by the SF unit (SCISSOR_RECT) is
* stored as an array of up to 16 elements. The location of first
* element of the array, as specified by Pointer to SCISSOR_RECT, should
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