Mesa (master): 23 new commits

Sun Apr 11 16:42:22 UTC 2021

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=0dfc5b51967ea9645e22cf35f459a153dd85473d
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date:   Mon Mar 1 18:59:27 2021 -0500

    nv50/ir: fix emission of ld/st lock/unlock
    
    This is necessary to implement shared atomics.
    
    Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
    Acked-by: Pierre Moreau <dev at pmoreau.org>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9299>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=d0fa6e066b3c91be7196dc392b95dbf97445ac96
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date:   Mon Mar 1 18:57:56 2021 -0500

    nv50/ir: avoid inlining results of a locked load
    
    These are a bit special. Among other things, removing them will cause us
    to potentially remove the load itself, defeating the purpose of the
    locking. Also it's unclear whether it's legal to access the shared
    memory directly when it's locked like this.
    
    This only comes up on nv50, since on nvc0+, shared memory can't be
    loaded from random ops.
    
    Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
    Acked-by: Pierre Moreau <dev at pmoreau.org>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9299>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=7052927ee4420ead8b03f8e6489d2a92b14efc7f
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date:   Fri Feb 26 20:45:21 2021 -0500

    nv50: fix expression for ucp offset
    
    It doesn't matter since it's 0, but all the offsets are in bytes whereas
    the method expects words. So adjust by 2.
    
    Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
    Reviewed-by: Pierre Moreau <dev at pmoreau.org>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9299>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=52172fded5640d5f6257766275a7b4cf01ce7017
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date:   Sat Feb 27 18:24:44 2021 -0500

    nv50/ir: fix emission of cas without a destination
    
    We were previously dumping $r127 in there. This has a bad effect on
    nv50, so make sure we allocate an actual register for it, even if
    there's nothing using the result.
    
    Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
    Acked-by: Pierre Moreau <dev at pmoreau.org>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9299>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=a3b02fea7e54bb44f87a5986727fab8b1c4da641
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date:   Sun Feb 28 20:08:25 2021 -0500

    nv50/ir: fix emission of 16-bit add
    
    Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
    Acked-by: Pierre Moreau <dev at pmoreau.org>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9299>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=fe93723aaa16be29cc5b679e39fddd9683bf2839
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date:   Wed Feb 24 22:21:24 2021 -0500

    nv50/ir: add support for 16-bit immediates
    
    Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
    Reviewed-by: Pierre Moreau <dev at pmoreau.org>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9299>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=8a69efa171f25524668cea78c19b38d237494e42
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date:   Wed Feb 24 22:18:37 2021 -0500

    nv50/ir: logic ops on half-regs can't take an immediate
    
    There does not appear to be an instruction form for this. Prevent an
    immediate from being loaded into place.
    
    Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
    Reviewed-by: Pierre Moreau <dev at pmoreau.org>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9299>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=afcd296b1b8e93060b211ab59949eaff4c332bb8
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date:   Wed Feb 24 22:15:32 2021 -0500

    nv50/ir: fix emission of shifts on half-regs
    
    Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
    Acked-by: Pierre Moreau <dev at pmoreau.org>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9299>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=af8665c3a5bc91b2132c31e8ff619592f9472140
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date:   Wed Feb 24 22:15:04 2021 -0500

    nv50/ir: fix emission of logic ops on half-regs
    
    Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
    Acked-by: Pierre Moreau <dev at pmoreau.org>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9299>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=96e8e74813b142a1681c9eef49ca71d49db0502b
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date:   Wed Feb 24 22:14:16 2021 -0500

    nv50/ir: fix emission of cvt with half-reg destinations
    
    Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
    Acked-by: Pierre Moreau <dev at pmoreau.org>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9299>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=c6b02c097f7657e48a43da7c5f39b7b8baeff040
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date:   Wed Feb 24 14:17:55 2021 -0500

    nv50/ir: fix emitting movs from imm to short registers
    
    Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
    Acked-by: Pierre Moreau <dev at pmoreau.org>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9299>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=2ff2d65799e4a8351e99bab306bc49c01062ac19
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date:   Mon Feb 15 12:24:54 2021 -0500

    nv50/ir: lower buffer to global
    
    The idea is that buffers will be bound to the appropriate indices. That
    means that we can just rename them to global.
    
    Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
    Acked-by: Pierre Moreau <dev at pmoreau.org>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9299>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=ee28cae1ef1cf0d965e7cafe3fc3be1e83736bfb
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date:   Mon Feb 15 12:22:02 2021 -0500

    nv50/ir: fix emission of RED
    
    When the atomic result is unused, the opcode form needs to be a bit
    different.
    
    Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
    Acked-by: Pierre Moreau <dev at pmoreau.org>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9299>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=1fad964553622252a27818ad6ee58d5d826a74d8
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date:   Mon Mar 1 19:51:14 2021 -0500

    nv50/ir: do not use inline offsets for global, ensure indirect access
    
    Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
    Reviewed-by: Pierre Moreau <dev at pmoreau.org>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9299>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=3e99271163f1e07758d43bddb9ff1be6576a186b
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date:   Thu Feb 25 23:08:00 2021 -0500

    nv50/ir: force shared memory indirect to be an address
    
    The upstream logic will not end up using an address, so we have to force
    it here. The other backends don't care either.
    
    Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
    Reviewed-by: Pierre Moreau <dev at pmoreau.org>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9299>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=d2a0aa5efedf36c30b27521dce00c1d70b905a56
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date:   Wed Feb 24 22:16:52 2021 -0500

    nv50/ir: retrieve (n)ctaid.z from first user param
    
    The driver is responsible for feeding this in.
    
    Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
    Reviewed-by: Pierre Moreau <dev at pmoreau.org>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9299>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=de71feccbfbc3f5e5f99c79e65f2a019e5ddcaa6
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date:   Wed Feb 24 19:34:05 2021 -0500

    nv50: pass in third axis via user param
    
    This is probably not the most efficient way to go for all geometries,
    but the assumption is that kernels tend to be x/y-heavy rather than
    z-heavy. Iterates over each z slice and passes in the current value via
    user param. (And bump all user params by a dword.)
    
    Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
    Reviewed-by: Pierre Moreau <dev at pmoreau.org>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9299>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=c3e9be9b5a55f2e1462463d680e48a1506196eac
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date:   Wed Feb 24 21:04:25 2021 -0500

    nv50: add texture, constbuf, image, buffer validation
    
    This makes compute mostly work. For now we're laying out images/buffers
    in a fixed offset from each other in the globals "array", but this
    should be done dynamically. We're also missing passing image info to
    shaders, as well as adding image formats to a shader key.
    
    Heavily inspired by nvc0 variants of these.
    
    Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
    Acked-by: Pierre Moreau <dev at pmoreau.org>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9299>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=1a6a772527974b390a5a691512319f7692ae430f
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date:   Wed Feb 24 19:42:03 2021 -0500

    nv50: implement memory barrier handling
    
    With shader images / buffers, we can get more complex barrier requests.
    This mirrors the logic in nvc0.
    
    Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
    Reviewed-by: Pierre Moreau <dev at pmoreau.org>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9299>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=cd296c9f8cc363088e63eda6092e146f061e9cdb
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date:   Wed Feb 24 19:29:57 2021 -0500

    nv50: add resource tracking for shader images and buffers
    
    Heavily inpsired by the nvc0 code. Note that these only exist for the
    compute stage, so there is no shared-based indexing.
    
    Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
    Reviewed-by: Pierre Moreau <dev at pmoreau.org>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9299>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=ba6ba8c9900eb1f8db14da3ebd77369b07e60857
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date:   Wed Feb 24 19:27:49 2021 -0500

    nv50: adapt texture and constbuf paths for compute shaders
    
    This contains the logic updates necessary to perform necessary resource
    tracking and emit update / flush commands for the relevant stages.
    
    Inspired by some changes from Pierre Moreau.
    
    Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
    Reviewed-by: Pierre Moreau <dev at pmoreau.org>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9299>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=9abfd4ba1839d88489fb245b3bd1a1e85f0d0cc2
Author: Pierre Moreau <dev at pmoreau.org>
Date:   Wed Jul 29 10:18:59 2020 +0200

    nv50: Update texture indices to match stage indices
    
    For legacy reasons, we were using the PIPE order, instead of the
    hardware order. Reorder the stages to match the order of the
    BIND_TIC/etc methods, and adjust internal usage to match.
    
    Signed-off-by: Pierre Moreau <dev at pmoreau.org>
    [imirkin: fixed numbering, removed TODO comments]
    
    Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9299>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=afe1472cde829a123c088f61ee26bdb7e176c0eb
Author: Pierre Moreau <dev at pmoreau.org>
Date:   Wed Jul 29 09:33:38 2020 +0200

    nv50: Replace hardcoded texture/constbuf count with define
    
    Signed-off-by: Pierre Moreau <dev at pmoreau.org>
    Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9299>