Mesa (master): include/drm-uapi: bump AMDGPU headers

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Module: Mesa
Branch: master
Commit: 012e84ac11e51c951f093e379e4160bac504094c
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=012e84ac11e51c951f093e379e4160bac504094c

Author: Leo Liu <leo.liu at amd.com>
Date:   Sat Apr  3 15:07:42 2021 -0400

include/drm-uapi: bump AMDGPU headers

>From drm-next:

commit 2cbcb78c9ee5520c8d836c7ff57d1b60ebe8e9b7
Merge: 06debd6e1b28 8c44390d8872
Author: Daniel Vetter <daniel.vetter at ffwll.ch>
Date:   Fri Mar 26 15:52:01 2021 +0100

    Merge tag 'amd-drm-next-5.13-2021-03-23' of https://gitlab.freedesktop.org/agd5f/linux into drm-next

    amd-drm-next-5.13-2021-03-23:

    amdgpu:
    ...

    UAPI:
    - amdgpu: Add a new INFO ioctl interface to query video capabilities
      rather than hardcoding them in userspace.  This allows us to provide
      fine grained asic capabilities (e.g., if a particular part is
      bandwidth limited, we can limit the capabilities).  Proposed userspace:
      https://gitlab.freedesktop.org/leoliu/drm/-/commits/info_video_caps
      https://gitlab.freedesktop.org/leoliu/mesa/-/commits/info_video_caps
    ...

    Danvet: A bunch of conflicts all over, but it seems to compile ... I
    did put the call to dc_allow_idle_optimizations() on a single line
    since it looked a bit too jarring to be left alone.

    Signed-off-by: Daniel Vetter <daniel.vetter at intel.com>
    From: Alex Deucher <alexander.deucher at amd.com>
    Link: https://patchwork.freedesktop.org/patch/msgid/20210324040147.1990338-1-alexander.deucher@amd.com

Signed-off-by: Leo Liu <leo.liu at amd.com>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10095>

---

 include/drm-uapi/amdgpu_drm.h | 34 ++++++++++++++++++++++++++++++++++
 1 file changed, 34 insertions(+)

diff --git a/include/drm-uapi/amdgpu_drm.h b/include/drm-uapi/amdgpu_drm.h
index 7fb9c09ee93..728566542f8 100644
--- a/include/drm-uapi/amdgpu_drm.h
+++ b/include/drm-uapi/amdgpu_drm.h
@@ -782,6 +782,12 @@ struct drm_amdgpu_cs_chunk_data {
 #define AMDGPU_INFO_VRAM_LOST_COUNTER		0x1F
 /* query ras mask of enabled features*/
 #define AMDGPU_INFO_RAS_ENABLED_FEATURES	0x20
+/* query video encode/decode caps */
+#define AMDGPU_INFO_VIDEO_CAPS			0x21
+	/* Subquery id: Decode */
+	#define AMDGPU_INFO_VIDEO_CAPS_DECODE		0
+	/* Subquery id: Encode */
+	#define AMDGPU_INFO_VIDEO_CAPS_ENCODE		1
 
 /* RAS MASK: UMC (VRAM) */
 #define AMDGPU_INFO_RAS_ENABLED_UMC			(1 << 0)
@@ -878,6 +884,10 @@ struct drm_amdgpu_info {
 		struct {
 			__u32 type;
 		} sensor_info;
+
+		struct {
+			__u32 type;
+		} video_cap;
 	};
 };
 
@@ -1074,6 +1084,30 @@ struct drm_amdgpu_info_vce_clock_table {
 	__u32 pad;
 };
 
+/* query video encode/decode caps */
+#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2			0
+#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4			1
+#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1			2
+#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC		3
+#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC			4
+#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG			5
+#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9			6
+#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1			7
+#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_COUNT			8
+
+struct drm_amdgpu_info_video_codec_info {
+	__u32 valid;
+	__u32 max_width;
+	__u32 max_height;
+	__u32 max_pixels_per_frame;
+	__u32 max_level;
+	__u32 pad;
+};
+
+struct drm_amdgpu_info_video_caps {
+	struct drm_amdgpu_info_video_codec_info codec_info[AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_COUNT];
+};
+
 /*
  * Supported GPU families
  */