Mesa (master): turnip: initialize pipeline->rb_{stencil,depth}_cntl always

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Module: Mesa
Branch: master
Commit: 43ebba4e8838a63ec5b8456b4a21843b0edca4f0
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=43ebba4e8838a63ec5b8456b4a21843b0edca4f0

Author: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
Date:   Thu Feb 11 07:53:06 2021 +0100

turnip: initialize pipeline->rb_{stencil,depth}_cntl always

This change will simplify further changes on LRZ state management.

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
Reviewed-by: Eric Anholt <eric at anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8615>

---

 src/freedreno/vulkan/tu_pipeline.c | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/src/freedreno/vulkan/tu_pipeline.c b/src/freedreno/vulkan/tu_pipeline.c
index e8326c6bfdf..360992b0dbb 100644
--- a/src/freedreno/vulkan/tu_pipeline.c
+++ b/src/freedreno/vulkan/tu_pipeline.c
@@ -2683,16 +2683,14 @@ tu_pipeline_builder_parse_depth_stencil(struct tu_pipeline_builder *builder,
    if (tu_pipeline_static_state(pipeline, &cs, TU_DYNAMIC_STATE_RB_DEPTH_CNTL, 2)) {
       tu_cs_emit_pkt4(&cs, REG_A6XX_RB_DEPTH_CNTL, 1);
       tu_cs_emit(&cs, rb_depth_cntl);
-   } else {
-      pipeline->rb_depth_cntl = rb_depth_cntl;
    }
+   pipeline->rb_depth_cntl = rb_depth_cntl;
 
    if (tu_pipeline_static_state(pipeline, &cs, TU_DYNAMIC_STATE_RB_STENCIL_CNTL, 2)) {
       tu_cs_emit_pkt4(&cs, REG_A6XX_RB_STENCIL_CONTROL, 1);
       tu_cs_emit(&cs, rb_stencil_cntl);
-   } else {
-      pipeline->rb_stencil_cntl = rb_stencil_cntl;
    }
+   pipeline->rb_stencil_cntl = rb_stencil_cntl;
 
    /* the remaining draw states arent used if there is no d/s, leave them empty */
    if (builder->depth_attachment_format == VK_FORMAT_UNDEFINED)