Mesa (master): intel/fs: Use CHV/BXT implementation of 64-bit MOV_INDIRECT on XeHP+.

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Module: Mesa
Branch: master
Commit: 05cce1f97d87cff14f7e869f4fa5bd39d3faef29
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=05cce1f97d87cff14f7e869f4fa5bd39d3faef29

Author: Francisco Jerez <currojerez at riseup.net>
Date:   Fri Dec  7 14:27:24 2018 -0800

intel/fs: Use CHV/BXT implementation of 64-bit MOV_INDIRECT on XeHP+.

According to the hardware spec "Vx1 and VxH indirect addressing for
Float, Half-Float, Double-Float and Quad-Word data must not be used."

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10000>

---

 src/intel/compiler/brw_fs_generator.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/intel/compiler/brw_fs_generator.cpp b/src/intel/compiler/brw_fs_generator.cpp
index 938133bd77a..f3799b15ed6 100644
--- a/src/intel/compiler/brw_fs_generator.cpp
+++ b/src/intel/compiler/brw_fs_generator.cpp
@@ -551,7 +551,7 @@ fs_generator::generate_mov_indirect(fs_inst *inst,
       if (type_sz(reg.type) > 4 &&
           ((devinfo->ver == 7 && !devinfo->is_haswell) ||
            devinfo->is_cherryview || gen_device_info_is_9lp(devinfo) ||
-           !devinfo->has_64bit_float)) {
+           !devinfo->has_64bit_float || devinfo->verx10 >= 125)) {
          /* IVB has an issue (which we found empirically) where it reads two
           * address register components per channel for indirectly addressed
           * 64-bit sources.