Mesa (master): intel/eu: Allow 64-bit registers on XeHP.

[GitLab Mirror]

Module: Mesa
Branch: master
Commit: 02ce55d2b19b91503eaa4b12894f757fb9a3bc71
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=02ce55d2b19b91503eaa4b12894f757fb9a3bc71

Author: Jordan Justen <jordan.l.justen at intel.com>
Date:   Tue Apr  6 13:10:29 2021 -0700

intel/eu: Allow 64-bit registers on XeHP.

Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10000>

---

 src/intel/compiler/brw_reg_type.c | 55 ++++++++++++++++++++++++++++++++++-----
 1 file changed, 49 insertions(+), 6 deletions(-)

diff --git a/src/intel/compiler/brw_reg_type.c b/src/intel/compiler/brw_reg_type.c
index b81fde56cf9..fb1124e2530 100644
--- a/src/intel/compiler/brw_reg_type.c
+++ b/src/intel/compiler/brw_reg_type.c
@@ -174,6 +174,24 @@ static const struct hw_type {
    [BRW_REGISTER_TYPE_HF] = { GFX12_HW_REG_TYPE_FLOAT(1), GFX12_HW_REG_TYPE_FLOAT(1) },
    [BRW_REGISTER_TYPE_VF] = { INVALID,                    GFX12_HW_REG_TYPE_FLOAT(0) },
 
+   [BRW_REGISTER_TYPE_D]  = { GFX12_HW_REG_TYPE_SINT(2),  GFX12_HW_REG_TYPE_SINT(2)  },
+   [BRW_REGISTER_TYPE_UD] = { GFX12_HW_REG_TYPE_UINT(2),  GFX12_HW_REG_TYPE_UINT(2)  },
+   [BRW_REGISTER_TYPE_W]  = { GFX12_HW_REG_TYPE_SINT(1),  GFX12_HW_REG_TYPE_SINT(1)  },
+   [BRW_REGISTER_TYPE_UW] = { GFX12_HW_REG_TYPE_UINT(1),  GFX12_HW_REG_TYPE_UINT(1)  },
+   [BRW_REGISTER_TYPE_B]  = { GFX12_HW_REG_TYPE_SINT(0),  INVALID                    },
+   [BRW_REGISTER_TYPE_UB] = { GFX12_HW_REG_TYPE_UINT(0),  INVALID                    },
+   [BRW_REGISTER_TYPE_V]  = { INVALID,                    GFX12_HW_REG_TYPE_SINT(0)  },
+   [BRW_REGISTER_TYPE_UV] = { INVALID,                    GFX12_HW_REG_TYPE_UINT(0)  },
+}, gfx125_hw_type[] = {
+   [0 ... BRW_REGISTER_TYPE_LAST] = {            INVALID, INVALID                    },
+
+   [BRW_REGISTER_TYPE_DF] = { GFX12_HW_REG_TYPE_FLOAT(3), GFX12_HW_REG_TYPE_FLOAT(3) },
+   [BRW_REGISTER_TYPE_F]  = { GFX12_HW_REG_TYPE_FLOAT(2), GFX12_HW_REG_TYPE_FLOAT(2) },
+   [BRW_REGISTER_TYPE_HF] = { GFX12_HW_REG_TYPE_FLOAT(1), GFX12_HW_REG_TYPE_FLOAT(1) },
+   [BRW_REGISTER_TYPE_VF] = { INVALID,                    GFX12_HW_REG_TYPE_FLOAT(0) },
+
+   [BRW_REGISTER_TYPE_Q]  = { GFX12_HW_REG_TYPE_SINT(3),  GFX12_HW_REG_TYPE_SINT(3)  },
+   [BRW_REGISTER_TYPE_UQ] = { GFX12_HW_REG_TYPE_UINT(3),  GFX12_HW_REG_TYPE_UINT(3)  },
    [BRW_REGISTER_TYPE_D]  = { GFX12_HW_REG_TYPE_SINT(2),  GFX12_HW_REG_TYPE_SINT(2)  },
    [BRW_REGISTER_TYPE_UD] = { GFX12_HW_REG_TYPE_UINT(2),  GFX12_HW_REG_TYPE_UINT(2)  },
    [BRW_REGISTER_TYPE_W]  = { GFX12_HW_REG_TYPE_SINT(1),  GFX12_HW_REG_TYPE_SINT(1)  },
@@ -272,6 +290,21 @@ static const struct hw_3src_type {
    [BRW_REGISTER_TYPE_F]  = { GFX12_HW_REG_TYPE_UINT(2),     E(FLOAT), },
    [BRW_REGISTER_TYPE_HF] = { GFX12_HW_REG_TYPE_UINT(1),     E(FLOAT), },
 
+   [BRW_REGISTER_TYPE_D]  = { GFX12_HW_REG_TYPE_SINT(2),     E(INT),  },
+   [BRW_REGISTER_TYPE_UD] = { GFX12_HW_REG_TYPE_UINT(2),     E(INT),  },
+   [BRW_REGISTER_TYPE_W]  = { GFX12_HW_REG_TYPE_SINT(1),     E(INT),  },
+   [BRW_REGISTER_TYPE_UW] = { GFX12_HW_REG_TYPE_UINT(1),     E(INT),  },
+   [BRW_REGISTER_TYPE_B]  = { GFX12_HW_REG_TYPE_SINT(0),     E(INT),  },
+   [BRW_REGISTER_TYPE_UB] = { GFX12_HW_REG_TYPE_UINT(0),     E(INT),  },
+}, gfx125_hw_3src_type[] = {
+   [0 ... BRW_REGISTER_TYPE_LAST] = { INVALID },
+
+   [BRW_REGISTER_TYPE_DF] = { GFX12_HW_REG_TYPE_UINT(3),     E(FLOAT), },
+   [BRW_REGISTER_TYPE_F]  = { GFX12_HW_REG_TYPE_UINT(2),     E(FLOAT), },
+   [BRW_REGISTER_TYPE_HF] = { GFX12_HW_REG_TYPE_UINT(1),     E(FLOAT), },
+
+   [BRW_REGISTER_TYPE_Q]  = { GFX12_HW_REG_TYPE_SINT(3),     E(INT),  },
+   [BRW_REGISTER_TYPE_UQ] = { GFX12_HW_REG_TYPE_UINT(3),     E(INT),  },
    [BRW_REGISTER_TYPE_D]  = { GFX12_HW_REG_TYPE_SINT(2),     E(INT),  },
    [BRW_REGISTER_TYPE_UD] = { GFX12_HW_REG_TYPE_UINT(2),     E(INT),  },
    [BRW_REGISTER_TYPE_W]  = { GFX12_HW_REG_TYPE_SINT(1),     E(INT),  },
@@ -293,7 +326,10 @@ brw_reg_type_to_hw_type(const struct gen_device_info *devinfo,
 {
    const struct hw_type *table;
 
-   if (devinfo->ver >= 12) {
+   if (devinfo->verx10 >= 125) {
+      assert(type < ARRAY_SIZE(gfx125_hw_type));
+      table = gfx125_hw_type;
+   } else if (devinfo->ver >= 12) {
       assert(type < ARRAY_SIZE(gfx12_hw_type));
       table = gfx12_hw_type;
    } else if (devinfo->ver >= 11) {
@@ -333,7 +369,9 @@ brw_hw_type_to_reg_type(const struct gen_device_info *devinfo,
 {
    const struct hw_type *table;
 
-   if (devinfo->ver >= 12) {
+   if (devinfo->verx10 >= 125) {
+      table = gfx125_hw_type;
+   } else if (devinfo->ver >= 12) {
       table = gfx12_hw_type;
    } else if (devinfo->ver >= 11) {
       table = gfx11_hw_type;
@@ -396,7 +434,10 @@ unsigned
 brw_reg_type_to_a1_hw_3src_type(const struct gen_device_info *devinfo,
                                 enum brw_reg_type type)
 {
-   if (devinfo->ver >= 12) {
+   if (devinfo->verx10 >= 125) {
+      assert(type < ARRAY_SIZE(gfx125_hw_3src_type));
+      return gfx125_hw_3src_type[type].reg_type;
+   } else if (devinfo->ver >= 12) {
       assert(type < ARRAY_SIZE(gfx12_hw_3src_type));
       return gfx12_hw_3src_type[type].reg_type;
    } else if (devinfo->ver >= 11) {
@@ -442,9 +483,11 @@ enum brw_reg_type
 brw_a1_hw_3src_type_to_reg_type(const struct gen_device_info *devinfo,
                                 unsigned hw_type, unsigned exec_type)
 {
-   const struct hw_3src_type *table = (devinfo->ver >= 12 ? gfx12_hw_3src_type :
-                                       devinfo->ver >= 11 ? gfx11_hw_3src_type :
-                                       gfx10_hw_3src_align1_type);
+   const struct hw_3src_type *table =
+      (devinfo->verx10 >= 125 ? gfx125_hw_3src_type :
+       devinfo->ver >= 12 ? gfx12_hw_3src_type :
+       devinfo->ver >= 11 ? gfx11_hw_3src_type :
+       gfx10_hw_3src_align1_type);
 
    for (enum brw_reg_type i = 0; i <= BRW_REGISTER_TYPE_LAST; i++) {
       if (table[i].reg_type == hw_type &&