Mesa (master): radeonsi: fix automatic DCC retiling after DCC clear and DCC decompression

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Module: Mesa
Branch: master
Commit: 4d7dd094e3607ad628847bf01b6ab92442f94d1b
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=4d7dd094e3607ad628847bf01b6ab92442f94d1b

Author: Marek Olšák <marek.olsak at amd.com>
Date:   Wed Apr 14 20:08:03 2021 -0400

radeonsi: fix automatic DCC retiling after DCC clear and DCC decompression

Fixes: d4f7962d48b - radeonsi: Add displayable DCC flushing without explicit flushes.

Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer at amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10261>

---

 src/gallium/drivers/radeonsi/si_blit.c  |  1 +
 src/gallium/drivers/radeonsi/si_clear.c |  2 +-
 src/gallium/drivers/radeonsi/si_state.c | 41 +++++++++++++++------------------
 src/gallium/drivers/radeonsi/si_state.h |  1 +
 4 files changed, 22 insertions(+), 23 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_blit.c b/src/gallium/drivers/radeonsi/si_blit.c
index 6f79adc7385..653dfc343e7 100644
--- a/src/gallium/drivers/radeonsi/si_blit.c
+++ b/src/gallium/drivers/radeonsi/si_blit.c
@@ -1374,6 +1374,7 @@ void si_decompress_dcc(struct si_context *sctx, struct si_texture *tex)
       si_clear_buffer(sctx, ptex, tex->surface.meta_offset,
                       tex->surface.meta_size, &clear_value, 4, SI_OP_SYNC_AFTER,
                       SI_COHERENCY_CB_META, SI_COMPUTE_CLEAR_METHOD);
+      si_mark_display_dcc_dirty(sctx, tex);
 
       /* Clearing DCC metadata requires flushing L2 and invalidating L2 metadata to make
        * the metadata visible to L2 caches. This is because clear_buffer uses plain stores
diff --git a/src/gallium/drivers/radeonsi/si_clear.c b/src/gallium/drivers/radeonsi/si_clear.c
index 82e7d2d428f..b6003d11921 100644
--- a/src/gallium/drivers/radeonsi/si_clear.c
+++ b/src/gallium/drivers/radeonsi/si_clear.c
@@ -667,7 +667,7 @@ static void si_fast_clear(struct si_context *sctx, unsigned *buffers,
          clear_types |= SI_CLEAR_TYPE_DCC;
 
          tex->separate_dcc_dirty = true;
-         tex->displayable_dcc_dirty = true;
+         si_mark_display_dcc_dirty(sctx, tex);
 
          /* DCC fast clear with MSAA should clear CMASK to 0xC. */
          if (tex->buffer.b.b.nr_samples >= 2 && tex->cmask_buffer) {
diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index 8f22a188e56..e10a3e83b03 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -2600,32 +2600,29 @@ static void si_dec_framebuffer_counters(const struct pipe_framebuffer_state *sta
    }
 }
 
-static void si_update_display_dcc_dirty(struct si_context *sctx)
+void si_mark_display_dcc_dirty(struct si_context *sctx, struct si_texture *tex)
 {
-   const struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
-   struct si_surface *surf;
-   struct si_texture *tex;
-   int i;
-
-   for (i = 0; i < state->nr_cbufs; i++) {
-      if (!state->cbufs[i])
-         continue;
+   if (!tex->surface.display_dcc_offset || tex->displayable_dcc_dirty)
+      return;
 
-      surf = (struct si_surface *)state->cbufs[i];
-      tex = (struct si_texture *)surf->base.texture;
+   if (!(tex->buffer.external_usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH)) {
+      struct hash_entry *entry = _mesa_hash_table_search(sctx->dirty_implicit_resources, tex);
+      if (!entry) {
+         struct pipe_resource *dummy = NULL;
+         pipe_resource_reference(&dummy, &tex->buffer.b.b);
+         _mesa_hash_table_insert(sctx->dirty_implicit_resources, tex, tex);
+      }
+   }
+   tex->displayable_dcc_dirty = true;
+}
 
-      if (!tex->surface.display_dcc_offset || tex->displayable_dcc_dirty)
-         continue;
+static void si_update_display_dcc_dirty(struct si_context *sctx)
+{
+   const struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
 
-      if (!(tex->buffer.external_usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH)) {
-         struct hash_entry *entry = _mesa_hash_table_search(sctx->dirty_implicit_resources, tex);
-         if (!entry) {
-            struct pipe_resource *dummy = NULL;
-            pipe_resource_reference(&dummy, &tex->buffer.b.b);
-            _mesa_hash_table_insert(sctx->dirty_implicit_resources, tex, tex);
-         }
-      }
-      tex->displayable_dcc_dirty = true;
+   for (unsigned i = 0; i < state->nr_cbufs; i++) {
+      if (state->cbufs[i])
+         si_mark_display_dcc_dirty(sctx, (struct si_texture *)state->cbufs[i]->texture);
    }
 }
 
diff --git a/src/gallium/drivers/radeonsi/si_state.h b/src/gallium/drivers/radeonsi/si_state.h
index bbe765579b7..ea31a2afd2a 100644
--- a/src/gallium/drivers/radeonsi/si_state.h
+++ b/src/gallium/drivers/radeonsi/si_state.h
@@ -540,6 +540,7 @@ struct pipe_sampler_view *si_create_sampler_view_custom(struct pipe_context *ctx
                                                         unsigned width0, unsigned height0,
                                                         unsigned force_level);
 void si_update_fb_dirtiness_after_rendering(struct si_context *sctx);
+void si_mark_display_dcc_dirty(struct si_context *sctx, struct si_texture *tex);
 void si_update_ps_iter_samples(struct si_context *sctx);
 void si_save_qbo_state(struct si_context *sctx, struct si_qbo_state *st);
 void si_restore_qbo_state(struct si_context *sctx, struct si_qbo_state *st);