Mesa (master): ir3: Improve cat1 modifier disassembly
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Mon Apr 19 16:32:39 UTC 2021
Module: Mesa
Branch: master
Commit: d48d43039afbe08d7ca1eb9bc778499438c350ff
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d48d43039afbe08d7ca1eb9bc778499438c350ff
Author: Connor Abbott <cwabbott0 at gmail.com>
Date: Fri Apr 16 14:07:44 2021 +0200
ir3: Improve cat1 modifier disassembly
Remove bit that shouldn't be part of (rptN), and rewrite the handling of
(even) and (pos_infinity) to uncover a missing (neg_infinity) modifier.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10291>
---
src/freedreno/ir3/instr-a3xx.h | 7 +++++++
src/freedreno/ir3/ir3.h | 3 +--
src/freedreno/ir3/ir3_cf.c | 2 +-
src/freedreno/ir3/ir3_compiler_nir.c | 2 +-
src/freedreno/ir3/ir3_lexer.l | 1 +
src/freedreno/ir3/ir3_parser.y | 6 ++++--
src/freedreno/ir3/ir3_postsched.c | 6 ++++--
src/freedreno/isa/ir3-cat1.xml | 24 +++++++++++++++---------
8 files changed, 34 insertions(+), 17 deletions(-)
diff --git a/src/freedreno/ir3/instr-a3xx.h b/src/freedreno/ir3/instr-a3xx.h
index 4fc1d51e565..b56983a3b2b 100644
--- a/src/freedreno/ir3/instr-a3xx.h
+++ b/src/freedreno/ir3/instr-a3xx.h
@@ -355,6 +355,13 @@ static inline int type_sint(type_t type)
return (type == TYPE_S32) || (type == TYPE_S16) || (type == TYPE_S8);
}
+typedef enum {
+ ROUND_ZERO = 0,
+ ROUND_EVEN = 1,
+ ROUND_POS_INF = 2,
+ ROUND_NEG_INF = 3,
+} round_t;
+
typedef union PACKED {
/* normal gpr or const src register: */
struct PACKED {
diff --git a/src/freedreno/ir3/ir3.h b/src/freedreno/ir3/ir3.h
index bc11f89b94b..87c81449587 100644
--- a/src/freedreno/ir3/ir3.h
+++ b/src/freedreno/ir3/ir3.h
@@ -108,8 +108,6 @@ struct ir3_register {
IR3_REG_SNEG = 0x100,
IR3_REG_SABS = 0x200,
IR3_REG_BNOT = 0x400,
- IR3_REG_EVEN = 0x800,
- IR3_REG_POS_INF= 0x1000,
/* (ei) flag, end-input? Set on last bary, presumably to signal
* that the shader needs no more input:
*/
@@ -264,6 +262,7 @@ struct ir3_instruction {
} cat0;
struct {
type_t src_type, dst_type;
+ round_t round;
} cat1;
struct {
enum {
diff --git a/src/freedreno/ir3/ir3_cf.c b/src/freedreno/ir3/ir3_cf.c
index 62014f8700a..d479bc10759 100644
--- a/src/freedreno/ir3/ir3_cf.c
+++ b/src/freedreno/ir3/ir3_cf.c
@@ -37,7 +37,7 @@ is_fp16_conv(struct ir3_instruction *instr)
/* disallow conversions that cannot be folded into
* alu instructions:
*/
- if (dst->flags & (IR3_REG_EVEN | IR3_REG_POS_INF))
+ if (instr->cat1.round != ROUND_ZERO)
return false;
if (dst->flags & (IR3_REG_RELATIV | IR3_REG_ARRAY))
diff --git a/src/freedreno/ir3/ir3_compiler_nir.c b/src/freedreno/ir3/ir3_compiler_nir.c
index b6a5e91e31f..8065c302b46 100644
--- a/src/freedreno/ir3/ir3_compiler_nir.c
+++ b/src/freedreno/ir3/ir3_compiler_nir.c
@@ -260,7 +260,7 @@ create_cov(struct ir3_context *ctx, struct ir3_instruction *src,
ir3_COV(ctx->block, src, src_type, dst_type);
if (op == nir_op_f2f16 || op == nir_op_f2f16_rtne)
- cov->regs[0]->flags |= IR3_REG_EVEN;
+ cov->cat1.round = ROUND_EVEN;
return cov;
}
diff --git a/src/freedreno/ir3/ir3_lexer.l b/src/freedreno/ir3/ir3_lexer.l
index 47edd07ee1e..568145af71e 100644
--- a/src/freedreno/ir3/ir3_lexer.l
+++ b/src/freedreno/ir3/ir3_lexer.l
@@ -125,6 +125,7 @@ static int parse_w(const char *str)
"(ul)" return TOKEN(T_UL);
"(even)" return TOKEN(T_EVEN);
"(pos_infinity)" return TOKEN(T_POS_INFINITY);
+"(neg_infinity)" return TOKEN(T_NEG_INFINITY);
"(ei)" return TOKEN(T_EI);
"(jp)" return TOKEN(T_JP);
"(sat)" return TOKEN(T_SAT);
diff --git a/src/freedreno/ir3/ir3_parser.y b/src/freedreno/ir3/ir3_parser.y
index 6498aec70a5..fc684a54159 100644
--- a/src/freedreno/ir3/ir3_parser.y
+++ b/src/freedreno/ir3/ir3_parser.y
@@ -334,6 +334,7 @@ static void print_token(FILE *file, int type, YYSTYPE value)
/* dst register flags */
%token <tok> T_EVEN
%token <tok> T_POS_INFINITY
+%token <tok> T_NEG_INFINITY
%token <tok> T_EI
%token <num> T_WRMASK
@@ -1113,8 +1114,9 @@ reg: T_REGISTER { $$ = new_reg($1, 0); }
const: T_CONSTANT { $$ = new_reg($1, IR3_REG_CONST); }
-dst_reg_flag: T_EVEN { rflags.flags |= IR3_REG_EVEN; }
-| T_POS_INFINITY { rflags.flags |= IR3_REG_POS_INF; }
+dst_reg_flag: T_EVEN { instr->cat1.round = ROUND_EVEN; }
+| T_POS_INFINITY { instr->cat1.round = ROUND_POS_INF; }
+| T_NEG_INFINITY { instr->cat1.round = ROUND_NEG_INF; }
| T_EI { rflags.flags |= IR3_REG_EI; }
| T_WRMASK { rflags.wrmask = $1; }
diff --git a/src/freedreno/ir3/ir3_postsched.c b/src/freedreno/ir3/ir3_postsched.c
index f2ff6a051a1..614f1bf2062 100644
--- a/src/freedreno/ir3/ir3_postsched.c
+++ b/src/freedreno/ir3/ir3_postsched.c
@@ -672,10 +672,12 @@ is_self_mov(struct ir3_instruction *instr)
if (instr->regs[0]->flags & IR3_REG_RELATIV)
return false;
+ if (instr->cat1.round != ROUND_ZERO)
+ return false;
+
if (instr->regs[1]->flags & (IR3_REG_CONST | IR3_REG_IMMED |
IR3_REG_RELATIV | IR3_REG_FNEG | IR3_REG_FABS |
- IR3_REG_SNEG | IR3_REG_SABS | IR3_REG_BNOT |
- IR3_REG_EVEN | IR3_REG_POS_INF))
+ IR3_REG_SNEG | IR3_REG_SABS | IR3_REG_BNOT))
return false;
return true;
diff --git a/src/freedreno/isa/ir3-cat1.xml b/src/freedreno/isa/ir3-cat1.xml
index e55c7357861..671ccd42e2b 100644
--- a/src/freedreno/isa/ir3-cat1.xml
+++ b/src/freedreno/isa/ir3-cat1.xml
@@ -60,16 +60,23 @@ SOFTWARE.
</encode>
</bitset>
+<enum name="#round">
+ <value val="0" display=""/>
+ <value val="1" display="(even)"/>
+ <value val="2" display="(pos_infinity)"/>
+ <value val="3" display="(neg_infinity)"/>
+</enum>
+
<bitset name="#instruction-cat1" extends="#instruction">
<field name="DST" low="32" high="39" type="#cat1-dst">
<param name="DST_REL"/>
</field>
- <field name="REPEAT" low="40" high="42" type="#rptN"/>
+ <field name="REPEAT" low="40" high="41" type="#rptN"/>
+ <pattern pos="42">0</pattern>
<field name="SS" pos="44" type="bool" display="(ss)"/>
<field name="UL" pos="45" type="bool" display="(ul)"/>
<field name="DST_REL" pos="49" type="bool"/>
- <field name="EVEN" pos="55" type="bool" display="(even)"/>
- <field name="POS_INF" pos="56" type="bool" display="(pos_infinity)"/>
+ <field name="ROUND" low="55" high="56" type="#round"/>
<field name="JP" pos="59" type="bool" display="(jp)"/>
<field name="SY" pos="60" type="bool" display="(sy)"/>
<pattern low="61" high="63">001</pattern> <!-- cat1 -->
@@ -80,8 +87,7 @@ SOFTWARE.
<map name="DST_TYPE">src->cat1.dst_type</map>
<map name="DST_REL">!!(src->regs[0]->flags & IR3_REG_RELATIV)</map>
<map name="SRC_TYPE">src->cat1.src_type</map>
- <map name="EVEN">!!(src->regs[0]->flags & IR3_REG_EVEN)</map>
- <map name="POS_INF">!!(src->regs[0]->flags & IR3_REG_POS_INF)</map>
+ <map name="ROUND">src->cat1.round</map>
</encode>
</bitset>
@@ -91,7 +97,7 @@ SOFTWARE.
({DST} == 0xf4 /* a0.x */) && ({SRC_TYPE} == 4 /* s16 */) && ({DST_TYPE} == 4)
</expr>
<display>
- {SY}{SS}{JP}{REPEAT}{UL}mova {EVEN}{POS_INF}a0.x, {SRC}
+ {SY}{SS}{JP}{REPEAT}{UL}mova {ROUND}a0.x, {SRC}
</display>
<assert low="32" high="39">11110100</assert> <!-- DST==a0.x -->
<assert low="46" high="48">100</assert> <!-- DST_TYPE==s16 -->
@@ -102,7 +108,7 @@ SOFTWARE.
({DST} == 0xf5 /* a0.y */) && ({SRC_TYPE} == 2 /* u16 */) && ({DST_TYPE} == 2)
</expr>
<display>
- {SY}{SS}{JP}{REPEAT}{UL}mova1 {EVEN}{POS_INF}a1.x, {SRC}
+ {SY}{SS}{JP}{REPEAT}{UL}mova1 {ROUND}a1.x, {SRC}
</display>
<assert low="32" high="39">11110101</assert> <!-- DST==a0.y -->
<assert low="46" high="48">010</assert> <!-- DST_TYPE==u16 -->
@@ -113,11 +119,11 @@ SOFTWARE.
{SRC_TYPE} != {DST_TYPE}
</expr>
<display>
- {SY}{SS}{JP}{REPEAT}{UL}cov.{SRC_TYPE}{DST_TYPE} {EVEN}{POS_INF}{DST_HALF}{DST}, {SRC}
+ {SY}{SS}{JP}{REPEAT}{UL}cov.{SRC_TYPE}{DST_TYPE} {ROUND}{DST_HALF}{DST}, {SRC}
</display>
</override>
<display>
- {SY}{SS}{JP}{REPEAT}{UL}mov.{SRC_TYPE}{DST_TYPE} {EVEN}{POS_INF}{DST_HALF}{DST}, {SRC}
+ {SY}{SS}{JP}{REPEAT}{UL}mov.{SRC_TYPE}{DST_TYPE} {ROUND}{DST_HALF}{DST}, {SRC}
</display>
<pattern low="57" high="58">00</pattern> <!-- OPC -->
<derived name="HALF" type="bool" display="h">
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