Mesa (master): ac/surface: Move drm_fourcc.h to common header
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Thu Apr 22 08:31:31 UTC 2021
Module: Mesa
Branch: master
Commit: a64b36ecafd6e0e80079b61f69871a1c7c6c2e43
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a64b36ecafd6e0e80079b61f69871a1c7c6c2e43
Author: James Park <jpark37 at lagfreegames.com>
Date: Thu Apr 22 00:48:31 2021 -0700
ac/surface: Move drm_fourcc.h to common header
Useful for including from RADV without copy/paste.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9709>
---
src/amd/common/ac_drm_fourcc.h | 80 ++++++++++++++++++++++++++++++++++++++++++
src/amd/common/ac_surface.c | 48 +------------------------
2 files changed, 81 insertions(+), 47 deletions(-)
diff --git a/src/amd/common/ac_drm_fourcc.h b/src/amd/common/ac_drm_fourcc.h
new file mode 100644
index 00000000000..80a76bdf4a8
--- /dev/null
+++ b/src/amd/common/ac_drm_fourcc.h
@@ -0,0 +1,80 @@
+/*
+ * Copyright © 2021 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
+ * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ */
+
+#ifndef AC_DRM_FOURCC_H
+#define AC_DRM_FOURCC_H
+
+#ifdef _WIN32
+#include <stdint.h>
+typedef uint64_t __u64;
+#define DRM_FORMAT_MOD_VENDOR_NONE 0
+#define DRM_FORMAT_MOD_VENDOR_AMD 0x02
+#define DRM_FORMAT_RESERVED ((1ULL << 56) - 1)
+#define fourcc_mod_code(vendor, val) \
+ ((((__u64)DRM_FORMAT_MOD_VENDOR_## vendor) << 56) | ((val) & 0x00ffffffffffffffULL))
+#define DRM_FORMAT_MOD_INVALID fourcc_mod_code(NONE, DRM_FORMAT_RESERVED)
+#define DRM_FORMAT_MOD_LINEAR fourcc_mod_code(NONE, 0)
+#define AMD_FMT_MOD fourcc_mod_code(AMD, 0)
+#define IS_AMD_FMT_MOD(val) (((val) >> 56) == DRM_FORMAT_MOD_VENDOR_AMD)
+#define AMD_FMT_MOD_TILE_VER_GFX9 1
+#define AMD_FMT_MOD_TILE_VER_GFX10 2
+#define AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS 3
+#define AMD_FMT_MOD_TILE_GFX9_64K_S 9
+#define AMD_FMT_MOD_TILE_GFX9_64K_D 10
+#define AMD_FMT_MOD_TILE_GFX9_64K_S_X 25
+#define AMD_FMT_MOD_TILE_GFX9_64K_D_X 26
+#define AMD_FMT_MOD_TILE_GFX9_64K_R_X 27
+#define AMD_FMT_MOD_DCC_BLOCK_64B 0
+#define AMD_FMT_MOD_DCC_BLOCK_128B 1
+#define AMD_FMT_MOD_TILE_VERSION_SHIFT 0
+#define AMD_FMT_MOD_TILE_SHIFT 8
+#define AMD_FMT_MOD_TILE_MASK 0x1F
+#define AMD_FMT_MOD_DCC_SHIFT 13
+#define AMD_FMT_MOD_DCC_MASK 0x1
+#define AMD_FMT_MOD_DCC_RETILE_SHIFT 14
+#define AMD_FMT_MOD_DCC_RETILE_MASK 0x1
+#define AMD_FMT_MOD_DCC_PIPE_ALIGN_SHIFT 15
+#define AMD_FMT_MOD_DCC_PIPE_ALIGN_MASK 0x1
+#define AMD_FMT_MOD_DCC_INDEPENDENT_64B_SHIFT 16
+#define AMD_FMT_MOD_DCC_INDEPENDENT_64B_MASK 0x1
+#define AMD_FMT_MOD_DCC_INDEPENDENT_128B_SHIFT 17
+#define AMD_FMT_MOD_DCC_INDEPENDENT_128B_MASK 0x1
+#define AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_SHIFT 18
+#define AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_MASK 0x3
+#define AMD_FMT_MOD_DCC_CONSTANT_ENCODE_SHIFT 20
+#define AMD_FMT_MOD_PIPE_XOR_BITS_SHIFT 21
+#define AMD_FMT_MOD_BANK_XOR_BITS_SHIFT 24
+#define AMD_FMT_MOD_PACKERS_SHIFT 27 /* aliases with BANK_XOR_BITS */
+#define AMD_FMT_MOD_RB_SHIFT 30
+#define AMD_FMT_MOD_PIPE_SHIFT 33
+#define AMD_FMT_MOD_SET(field, value) \
+ ((uint64_t)(value) << AMD_FMT_MOD_##field##_SHIFT)
+#define AMD_FMT_MOD_GET(field, value) \
+ (((value) >> AMD_FMT_MOD_##field##_SHIFT) & AMD_FMT_MOD_##field##_MASK)
+#else
+#include "drm-uapi/drm_fourcc.h"
+#endif
+
+#endif /* AC_DRM_FOURCC_H */
diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c
index b24a7591945..c20f9eb24cb 100644
--- a/src/amd/common/ac_surface.c
+++ b/src/amd/common/ac_surface.c
@@ -28,6 +28,7 @@
#define AC_SURFACE_INCLUDE_NIR
#include "ac_surface.h"
+#include "ac_drm_fourcc.h"
#include "ac_gpu_info.h"
#include "addrlib/inc/addrinterface.h"
#include "addrlib/src/amdgpu_asic_addr.h"
@@ -46,52 +47,6 @@
#include <stdlib.h>
#ifdef _WIN32
-typedef uint64_t __u64;
-#define DRM_FORMAT_MOD_VENDOR_NONE 0
-#define DRM_FORMAT_MOD_VENDOR_AMD 0x02
-#define DRM_FORMAT_RESERVED ((1ULL << 56) - 1)
-#define fourcc_mod_code(vendor, val) \
- ((((__u64)DRM_FORMAT_MOD_VENDOR_## vendor) << 56) | ((val) & 0x00ffffffffffffffULL))
-#define DRM_FORMAT_MOD_INVALID fourcc_mod_code(NONE, DRM_FORMAT_RESERVED)
-#define DRM_FORMAT_MOD_LINEAR fourcc_mod_code(NONE, 0)
-#define AMD_FMT_MOD fourcc_mod_code(AMD, 0)
-#define IS_AMD_FMT_MOD(val) (((val) >> 56) == DRM_FORMAT_MOD_VENDOR_AMD)
-#define AMD_FMT_MOD_TILE_VER_GFX9 1
-#define AMD_FMT_MOD_TILE_VER_GFX10 2
-#define AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS 3
-#define AMD_FMT_MOD_TILE_GFX9_64K_S 9
-#define AMD_FMT_MOD_TILE_GFX9_64K_D 10
-#define AMD_FMT_MOD_TILE_GFX9_64K_S_X 25
-#define AMD_FMT_MOD_TILE_GFX9_64K_D_X 26
-#define AMD_FMT_MOD_TILE_GFX9_64K_R_X 27
-#define AMD_FMT_MOD_DCC_BLOCK_64B 0
-#define AMD_FMT_MOD_DCC_BLOCK_128B 1
-#define AMD_FMT_MOD_TILE_VERSION_SHIFT 0
-#define AMD_FMT_MOD_TILE_SHIFT 8
-#define AMD_FMT_MOD_TILE_MASK 0x1F
-#define AMD_FMT_MOD_DCC_SHIFT 13
-#define AMD_FMT_MOD_DCC_MASK 0x1
-#define AMD_FMT_MOD_DCC_RETILE_SHIFT 14
-#define AMD_FMT_MOD_DCC_RETILE_MASK 0x1
-#define AMD_FMT_MOD_DCC_PIPE_ALIGN_SHIFT 15
-#define AMD_FMT_MOD_DCC_PIPE_ALIGN_MASK 0x1
-#define AMD_FMT_MOD_DCC_INDEPENDENT_64B_SHIFT 16
-#define AMD_FMT_MOD_DCC_INDEPENDENT_64B_MASK 0x1
-#define AMD_FMT_MOD_DCC_INDEPENDENT_128B_SHIFT 17
-#define AMD_FMT_MOD_DCC_INDEPENDENT_128B_MASK 0x1
-#define AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_SHIFT 18
-#define AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_MASK 0x3
-#define AMD_FMT_MOD_DCC_CONSTANT_ENCODE_SHIFT 20
-#define AMD_FMT_MOD_PIPE_XOR_BITS_SHIFT 21
-#define AMD_FMT_MOD_BANK_XOR_BITS_SHIFT 24
-#define AMD_FMT_MOD_PACKERS_SHIFT 27 /* aliases with BANK_XOR_BITS */
-#define AMD_FMT_MOD_RB_SHIFT 30
-#define AMD_FMT_MOD_PIPE_SHIFT 33
-#define AMD_FMT_MOD_SET(field, value) \
- ((uint64_t)(value) << AMD_FMT_MOD_##field##_SHIFT)
-#define AMD_FMT_MOD_GET(field, value) \
- (((value) >> AMD_FMT_MOD_##field##_SHIFT) & AMD_FMT_MOD_##field##_MASK)
-
#define AMDGPU_TILING_ARRAY_MODE_SHIFT 0
#define AMDGPU_TILING_ARRAY_MODE_MASK 0xf
#define AMDGPU_TILING_PIPE_CONFIG_SHIFT 4
@@ -125,7 +80,6 @@ typedef uint64_t __u64;
#define AMDGPU_TILING_GET(value, field) \
(((__u64)(value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK)
#else
-#include "drm-uapi/drm_fourcc.h"
#include "drm-uapi/amdgpu_drm.h"
#endif
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