Mesa (master): radv: make sure CP DMA is idle before executing secondary command buffers

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Module: Mesa
Branch: master
Commit: 3d979c9169508b4f8e2bb0e925dde22dc34ed9bd
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=3d979c9169508b4f8e2bb0e925dde22dc34ed9bd

Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date:   Fri Apr 23 11:54:22 2021 +0200

radv: make sure CP DMA is idle before executing secondary command buffers

Buffer copies with CP DMA aren't synced.

Fix dEQP-VK.memory.pipeline_barrier.transfer_src_transfer_dst.65536
flakes on GFX10+.

Fixes: e8707961134 ("radv: prefer CP DMA for GTT buffer copies/clears on dGPUs due to slow PCIe")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10427>

---

 src/amd/vulkan/radv_cmd_buffer.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 1d9646b461f..4e6d33dc6ac 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -4743,6 +4743,9 @@ radv_CmdExecuteCommands(VkCommandBuffer commandBuffer, uint32_t commandBufferCou
    /* Emit pending flushes on primary prior to executing secondary */
    si_emit_cache_flush(primary);
 
+   /* Make sure CP DMA is idle on primary prior to executing secondary. */
+   si_cp_dma_wait_for_idle(primary);
+
    for (uint32_t i = 0; i < commandBufferCount; i++) {
       RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);