Mesa (main): radv: fix missing cache flushes when clearing HTILE levels on GFX10+

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Module: Mesa
Branch: main
Commit: ad83c06a5f880a1d836e17ef76e7382eb9b6222b
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=ad83c06a5f880a1d836e17ef76e7382eb9b6222b

Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date:   Mon Aug  2 16:43:15 2021 +0200

radv: fix missing cache flushes when clearing HTILE levels on GFX10+

The driver should accumulate the cache flush bits because if it uses
CP DMA for clearing the last level, it won't flush.

Found by inspection.

Cc: 21.2 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12170>

---

 src/amd/vulkan/radv_meta_clear.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/amd/vulkan/radv_meta_clear.c b/src/amd/vulkan/radv_meta_clear.c
index 3ad4040fe1c..65543c0fdf9 100644
--- a/src/amd/vulkan/radv_meta_clear.c
+++ b/src/amd/vulkan/radv_meta_clear.c
@@ -1389,10 +1389,10 @@ radv_clear_htile(struct radv_cmd_buffer *cmd_buffer, const struct radv_image *im
 
          if (htile_mask == UINT_MAX) {
             /* Clear the whole HTILE buffer. */
-            flush_bits = radv_fill_buffer(cmd_buffer, image, image->bo, offset, size, value);
+            flush_bits |= radv_fill_buffer(cmd_buffer, image, image->bo, offset, size, value);
          } else {
             /* Only clear depth or stencil bytes in the HTILE buffer. */
-            flush_bits =
+            flush_bits |=
                clear_htile_mask(cmd_buffer, image, image->bo, offset, size, value, htile_mask);
          }
       }