Mesa (staging/21.2): intel/compiler: make sure swizzle is applied to if condition

[GitLab Mirror]

Module: Mesa
Branch: staging/21.2
Commit: 7deef80ef6af70ac60c20b9873acd7909f8f11be
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=7deef80ef6af70ac60c20b9873acd7909f8f11be

Author: Timothy Arceri <tarceri at itsqueeze.com>
Date:   Thu Jul 29 12:14:16 2021 +1000

intel/compiler: make sure swizzle is applied to if condition

This fixes a hang in the following piglit test when GCM moves a
UBO load outside of the loop.

tests/shaders/ssa/fs-if-def-else-break.shader_test

The end NIR ends up looking like this:

	vec2 32 ssa_3 = intrinsic load_ubo (ssa_2, ssa_0) (0, 1073741824, 0, 0, 8)
	vec1 32 ssa_4 = mov ssa_3.x
	vec1 32 ssa_5 = inot ssa_3.y
	/* succs: block_1 */
	loop {
           ...
           if ssa_5 { }
        }

Fixes: 1edf67fc3f6b ("intel/fs: Generate if instructions with inverted conditions")

Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12064>
(cherry picked from commit a654e39f1559edc06eb12bdd6f2372694dcd8911)

---

 .pick_status.json                 | 2 +-
 src/intel/compiler/brw_fs_nir.cpp | 1 +
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/.pick_status.json b/.pick_status.json
index 8df42ed3185..c42c5177853 100644
--- a/.pick_status.json
+++ b/.pick_status.json
@@ -193,7 +193,7 @@
         "description": "intel/compiler: make sure swizzle is applied to if condition",
         "nominated": true,
         "nomination_type": 1,
-        "resolution": 0,
+        "resolution": 1,
         "main_sha": null,
         "because_sha": "1edf67fc3f6b944935506146de02348afa1003ff"
     },
diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp
index f0ec7dc839b..2f009977818 100644
--- a/src/intel/compiler/brw_fs_nir.cpp
+++ b/src/intel/compiler/brw_fs_nir.cpp
@@ -359,6 +359,7 @@ fs_visitor::nir_emit_if(nir_if *if_stmt)
    if (cond != NULL && cond->op == nir_op_inot) {
       invert = true;
       cond_reg = get_nir_src(cond->src[0].src);
+      cond_reg = offset(cond_reg, bld, cond->src[0].swizzle[0]);
    } else {
       invert = false;
       cond_reg = get_nir_src(if_stmt->condition);