Mesa (staging/21.2): radv: Write RSRC2_GS for NGGC when pipeline is dirty but not emitted.
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Fri Aug 6 17:27:11 UTC 2021
Module: Mesa
Branch: staging/21.2
Commit: 8d64d80d0a277e5e157d48845dcf1c2d80c2de1a
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=8d64d80d0a277e5e157d48845dcf1c2d80c2de1a
Author: Timur Kristóf <timur.kristof at gmail.com>
Date: Fri Aug 6 11:07:54 2021 +0200
radv: Write RSRC2_GS for NGGC when pipeline is dirty but not emitted.
The radv_emit_ngg_culling_state function won't write the
SPI_SHADER_PGM_RSRC2_GS register when it knows in advance that
radv_emit_graphics_pipeline will overwrite it anyway.
However, there is an unhandled case:
radv_emit_graphics_pipeline will not emit anything (including this
register) when the pipeline is already emitted. Hence, improve
the check in radv_emit_ngg_culling_state to consider this.
Fixes: 9a95f5487f5ab83fa44bea12afa30cf1a25fc9db
Signed-off-by: Timur Kristóf <timur.kristof at gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12237>
(cherry picked from commit 74181ffcc5ebed79916d3374455ccfa9e4efa05c)
---
.pick_status.json | 2 +-
src/amd/vulkan/radv_cmd_buffer.c | 7 +++++--
2 files changed, 6 insertions(+), 3 deletions(-)
diff --git a/.pick_status.json b/.pick_status.json
index c7878a55f27..4424f02be7e 100644
--- a/.pick_status.json
+++ b/.pick_status.json
@@ -76,7 +76,7 @@
"description": "radv: Write RSRC2_GS for NGGC when pipeline is dirty but not emitted.",
"nominated": true,
"nomination_type": 1,
- "resolution": 0,
+ "resolution": 1,
"main_sha": null,
"because_sha": "9a95f5487f5ab83fa44bea12afa30cf1a25fc9db"
},
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index b68e0796a68..2210ef62710 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -5838,8 +5838,11 @@ radv_emit_ngg_culling_state(struct radv_cmd_buffer *cmd_buffer, const struct rad
rsrc2 = (rsrc2 & C_00B22C_LDS_SIZE) | S_00B22C_LDS_SIZE(v->info.num_lds_blocks_when_not_culling);
}
- /* When the pipeline is dirty, radv_emit_graphics_pipeline will write this register. */
- if (!(cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)) {
+ /* When the pipeline is dirty and not yet emitted, don't write it here
+ * because radv_emit_graphics_pipeline will overwrite this register.
+ */
+ if (!(cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) ||
+ cmd_buffer->state.emitted_pipeline == pipeline) {
radeon_set_sh_reg(cmd_buffer->cs, R_00B22C_SPI_SHADER_PGM_RSRC2_GS, rsrc2);
}
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