Mesa (staging/21.2): radv: fix initializing the DS clear metadata value for separate aspects

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Module: Mesa
Branch: staging/21.2
Commit: c63674ee712a63c2f72bfc515fdf78e5cfc8d590
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=c63674ee712a63c2f72bfc515fdf78e5cfc8d590

Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date:   Thu Aug  5 17:47:02 2021 +0200

radv: fix initializing the DS clear metadata value for separate aspects

We shouldn't overwrite the clear value of the other aspect (in case
separate depth/stencil layouts are used).

Found by inspection.

Cc: 21.2 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12222>
(cherry picked from commit 1db36422b974094fc7ced81b734143b4f4aec302)

---

 .pick_status.json                | 2 +-
 src/amd/vulkan/radv_cmd_buffer.c | 6 +-----
 2 files changed, 2 insertions(+), 6 deletions(-)

diff --git a/.pick_status.json b/.pick_status.json
index 5a22d9ea71c..b6df30d44d6 100644
--- a/.pick_status.json
+++ b/.pick_status.json
@@ -364,7 +364,7 @@
         "description": "radv: fix initializing the DS clear metadata value for separate aspects",
         "nominated": true,
         "nomination_type": 0,
-        "resolution": 0,
+        "resolution": 1,
         "main_sha": null,
         "because_sha": null
     },
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 2210ef62710..a5bfd8b13f4 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -6599,7 +6599,6 @@ static void
 radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image,
                       const VkImageSubresourceRange *range)
 {
-   VkImageAspectFlags aspects = VK_IMAGE_ASPECT_DEPTH_BIT;
    struct radv_cmd_state *state = &cmd_buffer->state;
    uint32_t htile_value = radv_get_htile_initial_value(cmd_buffer->device, image);
    VkClearDepthStencilValue value = {0};
@@ -6615,10 +6614,7 @@ radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer, struct radv_image *ima
 
    state->flush_bits |= radv_clear_htile(cmd_buffer, image, range, htile_value);
 
-   if (vk_format_has_stencil(image->vk_format))
-      aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
-
-   radv_set_ds_clear_metadata(cmd_buffer, image, range, value, aspects);
+   radv_set_ds_clear_metadata(cmd_buffer, image, range, value, range->aspectMask);
 
    if (radv_image_is_tc_compat_htile(image) && (range->aspectMask & VK_IMAGE_ASPECT_DEPTH_BIT)) {
       /* Initialize the TC-compat metada value to 0 because by