Mesa (staging/21.2): radv: flush caches before performing separate depth/stencil aspect init

[GitLab Mirror]

Module: Mesa
Branch: staging/21.2
Commit: 2c5f49cb3d561c587d41aafb9d886edf5ba60149
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=2c5f49cb3d561c587d41aafb9d886edf5ba60149

Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date:   Thu Aug  5 18:52:19 2021 +0200

radv: flush caches before performing separate depth/stencil aspect init

It's a RMW operation, also note that DB doesn't use L2 on GFX6-8.

Fixes test_clear_depth_stencil_view() and test_discard_resource() tests
from vkd3d-proton.

Cc: 21.2 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12223>
(cherry picked from commit 7ae3881a4bf989436b602b30b9a91602435e47a6)

---

 .pick_status.json                | 2 +-
 src/amd/vulkan/radv_cmd_buffer.c | 8 ++++++++
 2 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/.pick_status.json b/.pick_status.json
index 0d59e552a3f..bf40278577a 100644
--- a/.pick_status.json
+++ b/.pick_status.json
@@ -4,7 +4,7 @@
         "description": "radv: flush caches before performing separate depth/stencil aspect init",
         "nominated": true,
         "nomination_type": 0,
-        "resolution": 0,
+        "resolution": 1,
         "main_sha": null,
         "because_sha": null
     },
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 8ccda269e6f..c185cbe16c9 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -6614,6 +6614,14 @@ radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer, struct radv_image *ima
    state->flush_bits |=
       radv_src_access_flush(cmd_buffer, VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT, image);
 
+   if (image->planes[0].surface.has_stencil &&
+       !(range->aspectMask == (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT))) {
+      /* Flush caches before performing a separate aspect initialization because it's a
+       * read-modify-write operation.
+       */
+      state->flush_bits |= radv_dst_access_flush(cmd_buffer, VK_ACCESS_SHADER_READ_BIT, image);
+   }
+
    state->flush_bits |= radv_clear_htile(cmd_buffer, image, range, htile_value);
 
    radv_set_ds_clear_metadata(cmd_buffer, image, range, value, range->aspectMask);