Mesa (main): radv: add RADV_DCC_CLEAR_SINGLE

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Module: Mesa
Branch: main
Commit: c336c4b0cb93cc8e2ad9087caaa126ff9f13fb79
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=c336c4b0cb93cc8e2ad9087caaa126ff9f13fb79

Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date:   Wed Apr 28 13:53:35 2021 +0200

radv: add RADV_DCC_CLEAR_SINGLE

When DCC is cleared with that code, the hardware expects the clear
color value to be stored at the beginning of each 256B block in
the image.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10518>

---

 src/amd/vulkan/radv_meta_clear.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/amd/vulkan/radv_meta_clear.c b/src/amd/vulkan/radv_meta_clear.c
index 4b783b39b99..e88715f86e1 100644
--- a/src/amd/vulkan/radv_meta_clear.c
+++ b/src/amd/vulkan/radv_meta_clear.c
@@ -1421,6 +1421,7 @@ enum {
    RADV_DCC_CLEAR_1110 = 0x80808080U,
    RADV_DCC_CLEAR_1111 = 0xC0C0C0C0U,
    RADV_DCC_CLEAR_REG = 0x20202020U,
+   RADV_DCC_CLEAR_SINGLE = 0x10101010U,
 };
 
 static void