Mesa (staging/21.2): radv: Use correct signedness in misalign test.
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Tue Aug 10 18:17:01 UTC 2021
Module: Mesa
Branch: staging/21.2
Commit: 403e7213b28387e8e19af73cb002d3eea2285cb5
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=403e7213b28387e8e19af73cb002d3eea2285cb5
Author: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Date: Sun Aug 8 17:12:58 2021 +0200
radv: Use correct signedness in misalign test.
Lots of the MAX2 args end up subtracting two unsigned numbers, which
blows up when the result is negative.
Fixes: 4c99d6ff54b ("radv: flush L2 for images affected by the pipe misaligned issue on GFX10+")
Reviewed-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12272>
(cherry picked from commit b2b1e8e40a69bea59df3414d9f100b6bf809cd8e)
Conflicts:
src/amd/vulkan/radv_image.c
---
.pick_status.json | 2 +-
src/amd/vulkan/radv_image.c | 146 ++++++++++++++++++++++----------------------
2 files changed, 74 insertions(+), 74 deletions(-)
diff --git a/.pick_status.json b/.pick_status.json
index 923e8bd9c28..9d23995c23d 100644
--- a/.pick_status.json
+++ b/.pick_status.json
@@ -454,7 +454,7 @@
"description": "radv: Use correct signedness in misalign test.",
"nominated": true,
"nomination_type": 1,
- "resolution": 0,
+ "resolution": 1,
"main_sha": null,
"because_sha": "4c99d6ff54b2614b46d7e2252aa6c71c46045c16"
},
diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index 75cbb738800..f53c46059ea 100644
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -1299,6 +1299,79 @@ radv_image_alloc_values(const struct radv_device *device, struct radv_image *ima
}
}
+/* Determine if the image is affected by the pipe misaligned metadata issue
+ * which requires to invalidate L2.
+ */
+static bool
+radv_image_is_pipe_misaligned(const struct radv_device *device, const struct radv_image *image)
+{
+ struct radeon_info *rad_info = &device->physical_device->rad_info;
+ int log2_samples = util_logbase2(image->info.samples);
+
+ assert(rad_info->chip_class >= GFX10);
+
+ for (unsigned i = 0; i < image->plane_count; ++i) {
+ VkFormat fmt = vk_format_get_plane_format(image->vk_format, i);
+ int log2_bpp = util_logbase2(vk_format_get_blocksize(fmt));
+ int log2_bpp_and_samples;
+
+ if (rad_info->chip_class >= GFX10_3) {
+ log2_bpp_and_samples = log2_bpp + log2_samples;
+ } else {
+ if (vk_format_has_depth(image->vk_format) && image->info.array_size >= 8) {
+ log2_bpp = 2;
+ }
+
+ log2_bpp_and_samples = MIN2(6, log2_bpp + log2_samples);
+ }
+
+ int num_pipes = G_0098F8_NUM_PIPES(rad_info->gb_addr_config);
+ int overlap = MAX2(0, log2_bpp_and_samples + num_pipes - 8);
+
+ if (vk_format_has_depth(image->vk_format)) {
+ if (radv_image_is_tc_compat_htile(image) && overlap) {
+ return true;
+ }
+ } else {
+ int max_compressed_frags = G_0098F8_MAX_COMPRESSED_FRAGS(rad_info->gb_addr_config);
+ int log2_samples_frag_diff = MAX2(0, log2_samples - max_compressed_frags);
+ int samples_overlap = MIN2(log2_samples, overlap);
+
+ /* TODO: It shouldn't be necessary if the image has DCC but
+ * not readable by shader.
+ */
+ if ((radv_image_has_dcc(image) || radv_image_is_tc_compat_cmask(image)) &&
+ (samples_overlap > log2_samples_frag_diff)) {
+ return true;
+ }
+ }
+ }
+
+ return false;
+}
+
+static bool
+radv_image_is_l2_coherent(const struct radv_device *device, const struct radv_image *image)
+{
+ if (device->physical_device->rad_info.chip_class >= GFX10) {
+ return !device->physical_device->rad_info.tcc_rb_non_coherent &&
+ !radv_image_is_pipe_misaligned(device, image);
+ } else if (device->physical_device->rad_info.chip_class == GFX9) {
+ if (image->info.samples == 1 &&
+ (image->usage &
+ (VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT | VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT)) &&
+ !vk_format_has_stencil(image->vk_format)) {
+ /* Single-sample color and single-sample depth
+ * (not stencil) are coherent with shaders on
+ * GFX9.
+ */
+ return true;
+ }
+ }
+
+ return false;
+}
+
static void
radv_image_reset_layout(struct radv_image *image)
{
@@ -1527,79 +1600,6 @@ radv_select_modifier(const struct radv_device *dev, VkFormat format,
unreachable("App specified an invalid modifier");
}
-/* Determine if the image is affected by the pipe misaligned metadata issue
- * which requires to invalidate L2.
- */
-static bool
-radv_image_is_pipe_misaligned(const struct radv_device *device, const struct radv_image *image)
-{
- struct radeon_info *rad_info = &device->physical_device->rad_info;
- unsigned log2_samples = util_logbase2(image->info.samples);
-
- assert(rad_info->chip_class >= GFX10);
-
- for (unsigned i = 0; i < image->plane_count; ++i) {
- VkFormat fmt = vk_format_get_plane_format(image->vk_format, i);
- unsigned log2_bpp = util_logbase2(vk_format_get_blocksize(fmt));
- unsigned log2_bpp_and_samples;
-
- if (rad_info->chip_class >= GFX10_3) {
- log2_bpp_and_samples = log2_bpp + log2_samples;
- } else {
- if (vk_format_has_depth(image->vk_format) && image->info.array_size >= 8) {
- log2_bpp = 2;
- }
-
- log2_bpp_and_samples = MIN2(6, log2_bpp + log2_samples);
- }
-
- unsigned num_pipes = G_0098F8_NUM_PIPES(rad_info->gb_addr_config);
- int overlap = MAX2(0, log2_bpp_and_samples + num_pipes - 8);
-
- if (vk_format_has_depth(image->vk_format)) {
- if (radv_image_is_tc_compat_htile(image) && overlap) {
- return true;
- }
- } else {
- unsigned max_compressed_frags = G_0098F8_MAX_COMPRESSED_FRAGS(rad_info->gb_addr_config);
- int log2_samples_frag_diff = MAX2(0, log2_samples - max_compressed_frags);
- int samples_overlap = MIN2(log2_samples, overlap);
-
- /* TODO: It shouldn't be necessary if the image has DCC but
- * not readable by shader.
- */
- if ((radv_image_has_dcc(image) || radv_image_is_tc_compat_cmask(image)) &&
- (samples_overlap > log2_samples_frag_diff)) {
- return true;
- }
- }
- }
-
- return false;
-}
-
-static bool
-radv_image_is_l2_coherent(const struct radv_device *device, const struct radv_image *image)
-{
- if (device->physical_device->rad_info.chip_class >= GFX10) {
- return !device->physical_device->rad_info.tcc_rb_non_coherent &&
- !radv_image_is_pipe_misaligned(device, image);
- } else if (device->physical_device->rad_info.chip_class == GFX9) {
- if (image->info.samples == 1 &&
- (image->usage &
- (VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT | VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT)) &&
- !vk_format_has_stencil(image->vk_format)) {
- /* Single-sample color and single-sample depth
- * (not stencil) are coherent with shaders on
- * GFX9.
- */
- return true;
- }
- }
-
- return false;
-}
-
VkResult
radv_image_create(VkDevice _device, const struct radv_image_create_info *create_info,
const VkAllocationCallbacks *alloc, VkImage *pImage)
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