Mesa (main): radeon/vcn: Enable the AV1 decode p010 mode

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: ef0bfe2459a7aab77f978feb310acf3ae8337694
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=ef0bfe2459a7aab77f978feb310acf3ae8337694

Author: Leo Liu <leo.liu at amd.com>
Date:   Sat Aug  7 17:07:36 2021 -0400

radeon/vcn: Enable the AV1 decode p010 mode

It will still support 8 bits dithering mode decode.

Signed-off-by: Leo Liu <leo.liu at amd.com>
Reviewed-by: Boyuan Zhang <Boyuan.Zhang at amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12307>

---

 src/gallium/drivers/radeon/radeon_vcn_dec.c | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/src/gallium/drivers/radeon/radeon_vcn_dec.c b/src/gallium/drivers/radeon/radeon_vcn_dec.c
index ee6ff99fd5a..fc86daf37aa 100644
--- a/src/gallium/drivers/radeon/radeon_vcn_dec.c
+++ b/src/gallium/drivers/radeon/radeon_vcn_dec.c
@@ -853,14 +853,14 @@ static rvcn_dec_message_av1_t get_av1_msg(struct radeon_decoder *dec,
       }
    }
 
-   result.p010_mode = 0;
-   result.msb_mode = 0;
-   if (!pic->picture_parameter.bit_depth_idx) {
-      result.luma_10to8 = 0;
-      result.chroma_10to8 = 0;
-   } else {
-      result.luma_10to8 = 1;
-      result.chroma_10to8 = 1;
+   if (pic->picture_parameter.bit_depth_idx) {
+      if (target->buffer_format == PIPE_FORMAT_P010 || target->buffer_format == PIPE_FORMAT_P016) {
+         result.p010_mode = 1;
+         result.msb_mode = 1;
+      } else {
+         result.luma_10to8 = 1;
+         result.chroma_10to8 = 1;
+      }
    }
 
    result.preskip_segid = 0;