Mesa (main): intel/isl: Use uint64_t for computed byte offsets
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gitlab-mirror at kemper.freedesktop.org
Tue Aug 17 14:54:00 UTC 2021
Module: Mesa
Branch: main
Commit: 782f75cb526e44f24a5fb38278167c4c4e00675a
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=782f75cb526e44f24a5fb38278167c4c4e00675a
Author: Jason Ekstrand <jason at jlekstrand.net>
Date: Wed Jul 7 11:28:05 2021 -0500
intel/isl: Use uint64_t for computed byte offsets
This is mostly a bit of future-proofing. We never end up with offsets
that don't fit in 32 bits today because, thanks to driver limitations
caused by relocations, we don't allocate buffers bigger than 2GB today.
However, if we ever did, it's possible to create a surface on modern
platforms that consumes more than 4GB and we would end up with wrapping
in our offset calculations.
Acked-by: Ivan Briano <ivan.briano at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11765>
---
src/gallium/drivers/crocus/crocus_blt.c | 13 ++++++++-----
src/gallium/drivers/crocus/crocus_state.c | 19 +++++++++++--------
src/gallium/drivers/iris/iris_state.c | 5 +++--
src/intel/blorp/blorp_blit.c | 15 ++++++++-------
src/intel/blorp/blorp_clear.c | 3 ++-
src/intel/blorp/blorp_genX_exec.h | 4 ++--
src/intel/isl/isl.c | 22 +++++++++++-----------
src/intel/isl/isl.h | 16 ++++++++--------
src/intel/vulkan/anv_image.c | 5 +++--
src/intel/vulkan/genX_cmd_buffer.c | 2 +-
src/mesa/drivers/dri/i965/brw_blit.c | 25 ++++++++++++++-----------
src/mesa/drivers/dri/i965/brw_misc_state.c | 4 ++--
12 files changed, 73 insertions(+), 60 deletions(-)
diff --git a/src/gallium/drivers/crocus/crocus_blt.c b/src/gallium/drivers/crocus/crocus_blt.c
index fb194657a9b..d6eaa1513f7 100644
--- a/src/gallium/drivers/crocus/crocus_blt.c
+++ b/src/gallium/drivers/crocus/crocus_blt.c
@@ -66,13 +66,14 @@ blt_set_alpha_to_one(struct crocus_batch *batch,
for (uint32_t chunk_y = 0; chunk_y < height; chunk_y += max_chunk_size) {
const uint32_t chunk_w = MIN2(max_chunk_size, width - chunk_x);
const uint32_t chunk_h = MIN2(max_chunk_size, height - chunk_y);
- uint32_t tile_x, tile_y, offset;
+ uint32_t tile_x, tile_y;
+ uint64_t offset_B;
ASSERTED uint32_t z_offset_el, array_offset;
isl_tiling_get_intratile_offset_el(dst->surf.tiling,
cpp * 8, dst->surf.row_pitch_B,
dst->surf.array_pitch_el_rows,
chunk_x, chunk_y, 0, 0,
- &offset,
+ &offset_B,
&tile_x, &tile_y,
&z_offset_el, &array_offset);
assert(z_offset_el == 0);
@@ -83,7 +84,7 @@ blt_set_alpha_to_one(struct crocus_batch *batch,
xyblt.RasterOperation = 0xF0;
xyblt.DestinationPitch = pitch;
xyblt._32bppByteMask = 2;
- xyblt.DestinationBaseAddress = rw_bo(dst->bo, offset);
+ xyblt.DestinationBaseAddress = rw_bo(dst->bo, offset_B);
xyblt.DestinationX1Coordinate = tile_x;
xyblt.DestinationY1Coordinate = tile_y;
xyblt.DestinationX2Coordinate = tile_x + chunk_w;
@@ -320,8 +321,9 @@ static bool crocus_emit_blt(struct crocus_batch *batch,
const uint32_t chunk_w = MIN2(max_chunk_size, src_width - chunk_x);
const uint32_t chunk_h = MIN2(max_chunk_size, src_height - chunk_y);
+ uint64_t src_offset;
+ uint32_t src_tile_x, src_tile_y;
ASSERTED uint32_t z_offset_el, array_offset;
- uint32_t src_offset, src_tile_x, src_tile_y;
isl_tiling_get_intratile_offset_el(src->surf.tiling,
src_cpp * 8, src->surf.row_pitch_B,
src->surf.array_pitch_el_rows,
@@ -332,7 +334,8 @@ static bool crocus_emit_blt(struct crocus_batch *batch,
assert(z_offset_el == 0);
assert(array_offset == 0);
- uint32_t dst_offset, dst_tile_x, dst_tile_y;
+ uint64_t dst_offset;
+ uint32_t dst_tile_x, dst_tile_y;
isl_tiling_get_intratile_offset_el(dst->surf.tiling,
dst_cpp * 8, dst->surf.row_pitch_B,
dst->surf.array_pitch_el_rows,
diff --git a/src/gallium/drivers/crocus/crocus_state.c b/src/gallium/drivers/crocus/crocus_state.c
index 07f72c3609e..73ad5c2011c 100644
--- a/src/gallium/drivers/crocus/crocus_state.c
+++ b/src/gallium/drivers/crocus/crocus_state.c
@@ -2908,7 +2908,8 @@ crocus_create_surface(struct pipe_context *ctx,
crocus_resource_finish_aux_import(&screen->base, res);
memcpy(&surf->surf, &res->surf, sizeof(surf->surf));
- uint32_t temp_offset, temp_x, temp_y;
+ uint64_t temp_offset;
+ uint32_t temp_x, temp_y;
isl_surf_get_image_offset_B_tile_sa(&res->surf, tmpl->u.tex.level,
res->base.b.target == PIPE_TEXTURE_3D ? 0 : tmpl->u.tex.first_layer,
@@ -2954,7 +2955,8 @@ crocus_create_surface(struct pipe_context *ctx,
/* TODO: compressed pbo uploads aren't working here */
return NULL;
- uint32_t offset_B = 0, tile_x_sa = 0, tile_y_sa = 0;
+ uint64_t offset_B = 0;
+ uint32_t tile_x_sa = 0, tile_y_sa = 0;
if (view->base_level > 0) {
/* We can't rely on the hardware's miplevel selection with such
@@ -4950,7 +4952,8 @@ emit_surface_state(struct crocus_batch *batch,
const struct intel_device_info *devinfo = &batch->screen->devinfo;
struct isl_device *isl_dev = &batch->screen->isl_dev;
uint32_t reloc = RELOC_32BIT;
- uint32_t offset = res->offset, tile_x_sa = 0, tile_y_sa = 0;
+ uint64_t offset_B = res->offset;
+ uint32_t tile_x_sa = 0, tile_y_sa = 0;
if (writeable)
reloc |= RELOC_WRITE;
@@ -4961,7 +4964,7 @@ emit_surface_state(struct crocus_batch *batch,
isl_surf_get_image_surf(isl_dev, in_surf,
view->base_level, 0,
view->base_array_layer,
- &surf, &offset,
+ &surf, &offset_B,
&tile_x_sa, &tile_y_sa);
view->base_array_layer = 0;
view->base_level = 0;
@@ -4969,7 +4972,7 @@ emit_surface_state(struct crocus_batch *batch,
isl_surf_get_image_surf(isl_dev, in_surf,
view->base_level, view->base_array_layer,
0,
- &surf, &offset,
+ &surf, &offset_B,
&tile_x_sa, &tile_y_sa);
view->base_array_layer = 0;
view->base_level = 0;
@@ -4994,7 +4997,7 @@ emit_surface_state(struct crocus_batch *batch,
.view = view,
.address = crocus_state_reloc(batch,
addr_offset + isl_dev->ss.addr_offset,
- res->bo, offset, reloc),
+ res->bo, offset_B, reloc),
.aux_surf = aux_surf,
.aux_usage = aux_usage,
.aux_address = aux_offset,
@@ -7419,7 +7422,7 @@ crocus_upload_dirty_render_state(struct crocus_context *ice,
if (crocus_resource_level_has_hiz(zres, view.base_level)) {
info.hiz_usage = zres->aux.usage;
info.hiz_surf = &zres->aux.surf;
- uint32_t hiz_offset = 0;
+ uint64_t hiz_offset = 0;
#if GFX_VER == 6
/* HiZ surfaces on Sandy Bridge technically don't support
@@ -7444,7 +7447,7 @@ crocus_upload_dirty_render_state(struct crocus_context *ice,
info.stencil_aux_usage = sres->aux.usage;
info.stencil_surf = &sres->surf;
- uint32_t stencil_offset = 0;
+ uint64_t stencil_offset = 0;
#if GFX_VER == 6
/* Stencil surfaces on Sandy Bridge technically don't support
* mip-mapping. However, we can fake it by offsetting to the
diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c
index 4721a1a8ca6..9dfd6775d99 100644
--- a/src/gallium/drivers/iris/iris_state.c
+++ b/src/gallium/drivers/iris/iris_state.c
@@ -2531,7 +2531,7 @@ iris_create_surface(struct pipe_context *ctx,
};
struct isl_surf read_surf = res->surf;
- uint32_t read_surf_offset_B = 0;
+ uint64_t read_surf_offset_B = 0;
uint32_t read_surf_tile_x_sa = 0, read_surf_tile_y_sa = 0;
if (tex->target == PIPE_TEXTURE_3D && array_len == 1) {
/* The minimum array element field of the surface state structure is
@@ -2623,7 +2623,8 @@ iris_create_surface(struct pipe_context *ctx,
assert(view->levels == 1);
struct isl_surf isl_surf;
- uint32_t offset_B = 0, tile_x_el = 0, tile_y_el = 0;
+ uint64_t offset_B = 0;
+ uint32_t tile_x_el = 0, tile_y_el = 0;
bool ok = isl_surf_get_uncompressed_surf(&screen->isl_dev, &res->surf,
view, &isl_surf, view,
&offset_B, &tile_x_el, &tile_y_el);
diff --git a/src/intel/blorp/blorp_blit.c b/src/intel/blorp/blorp_blit.c
index 3aca393e732..ad83e1fe253 100644
--- a/src/intel/blorp/blorp_blit.c
+++ b/src/intel/blorp/blorp_blit.c
@@ -1589,12 +1589,12 @@ blorp_surf_convert_to_single_slice(const struct isl_device *isl_dev,
else
layer = info->view.base_array_layer;
- uint32_t byte_offset;
+ uint64_t offset_B;
isl_surf_get_image_surf(isl_dev, &info->surf,
info->view.base_level, layer, z,
&info->surf,
- &byte_offset, &info->tile_x_sa, &info->tile_y_sa);
- info->addr.offset += byte_offset;
+ &offset_B, &info->tile_x_sa, &info->tile_y_sa);
+ info->addr.offset += offset_B;
uint32_t tile_x_px, tile_y_px;
surf_get_intratile_offset_px(info, &tile_x_px, &tile_y_px);
@@ -2182,7 +2182,8 @@ shrink_surface_params(const struct isl_device *dev,
struct brw_blorp_surface_info *info,
double *x0, double *x1, double *y0, double *y1)
{
- uint32_t byte_offset, x_offset_sa, y_offset_sa, size;
+ uint64_t offset_B;
+ uint32_t x_offset_sa, y_offset_sa, size;
struct isl_extent2d px_size_sa;
int adjust;
@@ -2201,12 +2202,12 @@ shrink_surface_params(const struct isl_device *dev,
info->surf.format, info->surf.row_pitch_B,
info->surf.array_pitch_el_rows,
x_offset_sa, y_offset_sa, 0, 0,
- &byte_offset,
+ &offset_B,
&info->tile_x_sa, &info->tile_y_sa,
&tile_z_sa, &tile_a);
assert(tile_z_sa == 0 && tile_a == 0);
- info->addr.offset += byte_offset;
+ info->addr.offset += offset_B;
adjust = (int)info->tile_x_sa / px_size_sa.w - (int)*x0;
*x0 += adjust;
@@ -2621,7 +2622,7 @@ blorp_surf_convert_to_uncompressed(const struct isl_device *isl_dev,
info->z_offset = 0;
}
- uint32_t offset_B;
+ uint64_t offset_B;
ASSERTED bool ok =
isl_surf_get_uncompressed_surf(isl_dev, &info->surf, &info->view,
&info->surf, &info->view, &offset_B,
diff --git a/src/intel/blorp/blorp_clear.c b/src/intel/blorp/blorp_clear.c
index 994a2fc92a9..1190e39ad3c 100644
--- a/src/intel/blorp/blorp_clear.c
+++ b/src/intel/blorp/blorp_clear.c
@@ -1309,7 +1309,8 @@ blorp_ccs_ambiguate(struct blorp_batch *batch,
layer = 0;
}
- uint32_t offset_B, x_offset_el, y_offset_el;
+ uint64_t offset_B;
+ uint32_t x_offset_el, y_offset_el;
isl_surf_get_image_offset_B_tile_el(surf->aux_surf, level, layer, z,
&offset_B, &x_offset_el, &y_offset_el);
params.dst.addr.offset += offset_B;
diff --git a/src/intel/blorp/blorp_genX_exec.h b/src/intel/blorp/blorp_genX_exec.h
index 3089861c264..25213e456d3 100644
--- a/src/intel/blorp/blorp_genX_exec.h
+++ b/src/intel/blorp/blorp_genX_exec.h
@@ -1657,7 +1657,7 @@ blorp_emit_depth_stencil_config(struct blorp_batch *batch,
* anyway by manually offsetting to the specified miplevel.
*/
assert(info.hiz_surf->dim_layout == ISL_DIM_LAYOUT_GFX6_STENCIL_HIZ);
- uint32_t offset_B;
+ uint64_t offset_B;
isl_surf_get_image_offset_B_tile_sa(info.hiz_surf,
info.view->base_level, 0, 0,
&offset_B, NULL, NULL);
@@ -1683,7 +1683,7 @@ blorp_emit_depth_stencil_config(struct blorp_batch *batch,
* anyway by manually offsetting to the specified miplevel.
*/
assert(info.stencil_surf->dim_layout == ISL_DIM_LAYOUT_GFX6_STENCIL_HIZ);
- uint32_t offset_B;
+ uint64_t offset_B;
isl_surf_get_image_offset_B_tile_sa(info.stencil_surf,
info.view->base_level, 0, 0,
&offset_B, NULL, NULL);
diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
index 1d4afa580d9..205e4759fde 100644
--- a/src/intel/isl/isl.c
+++ b/src/intel/isl/isl.c
@@ -2655,7 +2655,7 @@ isl_surf_get_image_offset_B_tile_sa(const struct isl_surf *surf,
uint32_t level,
uint32_t logical_array_layer,
uint32_t logical_z_offset_px,
- uint32_t *offset_B,
+ uint64_t *offset_B,
uint32_t *x_offset_sa,
uint32_t *y_offset_sa)
{
@@ -2687,7 +2687,7 @@ isl_surf_get_image_offset_B_tile_el(const struct isl_surf *surf,
uint32_t level,
uint32_t logical_array_layer,
uint32_t logical_z_offset_px,
- uint32_t *offset_B,
+ uint64_t *offset_B,
uint32_t *x_offset_el,
uint32_t *y_offset_el)
{
@@ -2724,8 +2724,8 @@ isl_surf_get_image_range_B_tile(const struct isl_surf *surf,
uint32_t level,
uint32_t logical_array_layer,
uint32_t logical_z_offset_px,
- uint32_t *start_tile_B,
- uint32_t *end_tile_B)
+ uint64_t *start_tile_B,
+ uint64_t *end_tile_B)
{
uint32_t start_x_offset_el, start_y_offset_el;
uint32_t start_z_offset_el, start_array_slice;
@@ -2793,7 +2793,7 @@ isl_surf_get_image_surf(const struct isl_device *dev,
uint32_t logical_array_layer,
uint32_t logical_z_offset_px,
struct isl_surf *image_surf,
- uint32_t *offset_B,
+ uint64_t *offset_B,
uint32_t *x_offset_sa,
uint32_t *y_offset_sa)
{
@@ -2833,7 +2833,7 @@ isl_surf_get_uncompressed_surf(const struct isl_device *dev,
const struct isl_view *view,
struct isl_surf *ucompr_surf,
struct isl_view *ucompr_view,
- uint32_t *offset_B,
+ uint64_t *offset_B,
uint32_t *x_offset_el,
uint32_t *y_offset_el)
{
@@ -2948,7 +2948,7 @@ isl_tiling_get_intratile_offset_el(enum isl_tiling tiling,
uint32_t total_y_offset_el,
uint32_t total_z_offset_el,
uint32_t total_array_offset,
- uint32_t *tile_offset_B,
+ uint64_t *tile_offset_B,
uint32_t *x_offset_el,
uint32_t *y_offset_el,
uint32_t *z_offset_el,
@@ -2957,8 +2957,8 @@ isl_tiling_get_intratile_offset_el(enum isl_tiling tiling,
if (tiling == ISL_TILING_LINEAR) {
assert(bpb % 8 == 0);
assert(total_z_offset_el == 0 && total_array_offset == 0);
- *tile_offset_B = total_y_offset_el * row_pitch_B +
- total_x_offset_el * (bpb / 8);
+ *tile_offset_B = (uint64_t)total_y_offset_el * row_pitch_B +
+ (uint64_t)total_x_offset_el * (bpb / 8);
*x_offset_el = 0;
*y_offset_el = 0;
*z_offset_el = 0;
@@ -3006,8 +3006,8 @@ isl_tiling_get_intratile_offset_el(enum isl_tiling tiling,
y_offset_tl += (z_offset_tl + a_offset_tl) * array_pitch_tl_rows;
*tile_offset_B =
- y_offset_tl * tile_info.phys_extent_B.h * row_pitch_B +
- x_offset_tl * tile_info.phys_extent_B.h * tile_info.phys_extent_B.w;
+ (uint64_t)y_offset_tl * tile_info.phys_extent_B.h * row_pitch_B +
+ (uint64_t)x_offset_tl * tile_info.phys_extent_B.h * tile_info.phys_extent_B.w;
}
uint32_t
diff --git a/src/intel/isl/isl.h b/src/intel/isl/isl.h
index 241cd60ab0c..4e012df7cd4 100644
--- a/src/intel/isl/isl.h
+++ b/src/intel/isl/isl.h
@@ -2577,7 +2577,7 @@ isl_surf_get_image_offset_B_tile_sa(const struct isl_surf *surf,
uint32_t level,
uint32_t logical_array_layer,
uint32_t logical_z_offset_px,
- uint32_t *offset_B,
+ uint64_t *offset_B,
uint32_t *x_offset_sa,
uint32_t *y_offset_sa);
@@ -2597,7 +2597,7 @@ isl_surf_get_image_offset_B_tile_el(const struct isl_surf *surf,
uint32_t level,
uint32_t logical_array_layer,
uint32_t logical_z_offset_px,
- uint32_t *offset_B,
+ uint64_t *offset_B,
uint32_t *x_offset_el,
uint32_t *y_offset_el);
@@ -2619,8 +2619,8 @@ isl_surf_get_image_range_B_tile(const struct isl_surf *surf,
uint32_t level,
uint32_t logical_array_layer,
uint32_t logical_z_offset_px,
- uint32_t *start_tile_B,
- uint32_t *end_tile_B);
+ uint64_t *start_tile_B,
+ uint64_t *end_tile_B);
/**
* Create an isl_surf that represents a particular subimage in the surface.
@@ -2641,7 +2641,7 @@ isl_surf_get_image_surf(const struct isl_device *dev,
uint32_t logical_array_layer,
uint32_t logical_z_offset_px,
struct isl_surf *image_surf,
- uint32_t *offset_B,
+ uint64_t *offset_B,
uint32_t *x_offset_sa,
uint32_t *y_offset_sa);
@@ -2670,7 +2670,7 @@ isl_surf_get_uncompressed_surf(const struct isl_device *dev,
const struct isl_view *view,
struct isl_surf *uncompressed_surf,
struct isl_view *uncompressed_view,
- uint32_t *offset_B,
+ uint64_t *offset_B,
uint32_t *x_offset_el,
uint32_t *y_offset_el);
@@ -2706,7 +2706,7 @@ isl_tiling_get_intratile_offset_el(enum isl_tiling tiling,
uint32_t total_y_offset_el,
uint32_t total_z_offset_el,
uint32_t total_array_offset,
- uint32_t *tile_offset_B,
+ uint64_t *tile_offset_B,
uint32_t *x_offset_el,
uint32_t *y_offset_el,
uint32_t *z_offset_el,
@@ -2744,7 +2744,7 @@ isl_tiling_get_intratile_offset_sa(enum isl_tiling tiling,
uint32_t total_y_offset_sa,
uint32_t total_z_offset_sa,
uint32_t total_array_offset,
- uint32_t *tile_offset_B,
+ uint64_t *tile_offset_B,
uint32_t *x_offset_sa,
uint32_t *y_offset_sa,
uint32_t *z_offset_sa,
diff --git a/src/intel/vulkan/anv_image.c b/src/intel/vulkan/anv_image.c
index 8a94a226b96..da6bbe2e46f 100644
--- a/src/intel/vulkan/anv_image.c
+++ b/src/intel/vulkan/anv_image.c
@@ -1921,7 +1921,7 @@ void anv_GetImageSubresourceLayout(
if (subresource->mipLevel > 0 || subresource->arrayLayer > 0) {
assert(surface->isl.tiling == ISL_TILING_LINEAR);
- uint32_t offset_B;
+ uint64_t offset_B;
isl_surf_get_image_offset_B_tile_sa(&surface->isl,
subresource->mipLevel,
subresource->arrayLayer,
@@ -2586,7 +2586,8 @@ anv_image_fill_surface_state(struct anv_device *device,
const struct isl_surf *isl_surf = &surface->isl;
struct isl_surf tmp_surf;
- uint32_t offset_B = 0, tile_x_sa = 0, tile_y_sa = 0;
+ uint64_t offset_B = 0;
+ uint32_t tile_x_sa = 0, tile_y_sa = 0;
if (isl_format_is_compressed(surface->isl.format) &&
!isl_format_is_compressed(view.format)) {
/* We're creating an uncompressed view of a compressed surface. This
diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c
index 070e935b74d..4718afb9e8a 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -541,7 +541,7 @@ anv_image_init_aux_tt(struct anv_cmd_buffer *cmd_buffer,
logical_z_offset_px = 0;
}
- uint32_t slice_start_offset_B, slice_end_offset_B;
+ uint64_t slice_start_offset_B, slice_end_offset_B;
isl_surf_get_image_range_B_tile(isl_surf, level,
logical_array_layer,
logical_z_offset_px,
diff --git a/src/mesa/drivers/dri/i965/brw_blit.c b/src/mesa/drivers/dri/i965/brw_blit.c
index 0539b72ef93..626d3e1b93f 100644
--- a/src/mesa/drivers/dri/i965/brw_blit.c
+++ b/src/mesa/drivers/dri/i965/brw_blit.c
@@ -164,7 +164,7 @@ get_blit_intratile_offset_el(const struct brw_context *brw,
struct brw_mipmap_tree *mt,
uint32_t total_x_offset_el,
uint32_t total_y_offset_el,
- uint32_t *base_address_offset,
+ uint64_t *tile_offset_B,
uint32_t *x_offset_el,
uint32_t *y_offset_el)
{
@@ -173,7 +173,7 @@ get_blit_intratile_offset_el(const struct brw_context *brw,
mt->cpp * 8, mt->surf.row_pitch_B,
mt->surf.array_pitch_el_rows,
total_x_offset_el, total_y_offset_el, 0, 0,
- base_address_offset,
+ tile_offset_B,
x_offset_el, y_offset_el,
&z_offset_el, &array_offset);
assert(z_offset_el == 0);
@@ -190,12 +190,12 @@ get_blit_intratile_offset_el(const struct brw_context *brw,
* The offsets we get from ISL in the tiled case are already aligned.
* In the linear case, we need to do some of our own aligning.
*/
- uint32_t delta = *base_address_offset & 63;
+ uint32_t delta = *tile_offset_B & 63;
assert(delta % mt->cpp == 0);
- *base_address_offset -= delta;
+ *tile_offset_B -= delta;
*x_offset_el += delta / mt->cpp;
} else {
- assert(*base_address_offset % 4096 == 0);
+ assert(*tile_offset_B % 4096 == 0);
}
}
@@ -419,12 +419,14 @@ emit_miptree_blit(struct brw_context *brw,
const uint32_t chunk_w = MIN2(max_chunk_size, width - chunk_x);
const uint32_t chunk_h = MIN2(max_chunk_size, height - chunk_y);
- uint32_t src_offset, src_tile_x, src_tile_y;
+ uint64_t src_offset;
+ uint32_t src_tile_x, src_tile_y;
get_blit_intratile_offset_el(brw, src_mt,
src_x + chunk_x, src_y + chunk_y,
&src_offset, &src_tile_x, &src_tile_y);
- uint32_t dst_offset, dst_tile_x, dst_tile_y;
+ uint64_t dst_offset;
+ uint32_t dst_tile_x, dst_tile_y;
get_blit_intratile_offset_el(brw, dst_mt,
dst_x + chunk_x, dst_y + chunk_y,
&dst_offset, &dst_tile_x, &dst_tile_y);
@@ -759,10 +761,11 @@ brw_miptree_set_alpha_to_one(struct brw_context *brw,
const uint32_t chunk_w = MIN2(max_chunk_size, width - chunk_x);
const uint32_t chunk_h = MIN2(max_chunk_size, height - chunk_y);
- uint32_t offset, tile_x, tile_y;
+ uint64_t offset_B;
+ uint32_t tile_x, tile_y;
get_blit_intratile_offset_el(brw, mt,
x + chunk_x, y + chunk_y,
- &offset, &tile_x, &tile_y);
+ &offset_B, &tile_x, &tile_y);
BEGIN_BATCH_BLT_TILED(length, dst_y_tiled, false);
OUT_BATCH(CMD | (length - 2));
@@ -772,9 +775,9 @@ brw_miptree_set_alpha_to_one(struct brw_context *brw,
OUT_BATCH(SET_FIELD(y + chunk_y + chunk_h, BLT_Y) |
SET_FIELD(x + chunk_x + chunk_w, BLT_X));
if (devinfo->ver >= 8) {
- OUT_RELOC64(mt->bo, RELOC_WRITE, mt->offset + offset);
+ OUT_RELOC64(mt->bo, RELOC_WRITE, mt->offset + offset_B);
} else {
- OUT_RELOC(mt->bo, RELOC_WRITE, mt->offset + offset);
+ OUT_RELOC(mt->bo, RELOC_WRITE, mt->offset + offset_B);
}
OUT_BATCH(0xffffffff); /* white, but only alpha gets written */
ADVANCE_BATCH_TILED(dst_y_tiled, false);
diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c
index 04291d025e4..aae5748d765 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -394,7 +394,7 @@ brw_emit_depthbuffer(struct brw_context *brw)
if (info.hiz_usage == ISL_AUX_USAGE_HIZ) {
info.hiz_surf = &depth_mt->aux_buf->surf;
- uint32_t hiz_offset = 0;
+ uint64_t hiz_offset = 0;
if (devinfo->ver == 6) {
/* HiZ surfaces on Sandy Bridge technically don't support
* mip-mapping. However, we can fake it by offsetting to the
@@ -428,7 +428,7 @@ brw_emit_depthbuffer(struct brw_context *brw)
view.format = stencil_mt->surf.format;
}
- uint32_t stencil_offset = 0;
+ uint64_t stencil_offset = 0;
if (devinfo->ver == 6) {
/* Stencil surfaces on Sandy Bridge technically don't support
* mip-mapping. However, we can fake it by offsetting to the
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