Mesa (main): intel/compiler: Document and assert some aspects of 8-bit integer lowering
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Wed Aug 18 23:07:11 UTC 2021
Module: Mesa
Branch: main
Commit: f9665040f19d826f7932a2996ac46c69aea7e624
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f9665040f19d826f7932a2996ac46c69aea7e624
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Fri Jan 22 14:54:02 2021 -0800
intel/compiler: Document and assert some aspects of 8-bit integer lowering
In the vec4 compiler, 8-bit types should never exist.
In the scalar compiler, 8-bit types should only ever be able to exist on
Gfx ver 8 and 9.
Some instructions are handled in non-obvious ways.
Hopefully this will save the next person some time.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9025>
---
src/intel/compiler/brw_fs_nir.cpp | 33 +++++++++++++++++++++++++++++++++
src/intel/compiler/brw_nir.c | 8 ++++++++
src/intel/compiler/brw_vec4_nir.cpp | 8 ++++++++
3 files changed, 49 insertions(+)
diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp
index 06d180e309c..cf71e229806 100644
--- a/src/intel/compiler/brw_fs_nir.cpp
+++ b/src/intel/compiler/brw_fs_nir.cpp
@@ -965,6 +965,39 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr,
fs_reg op[NIR_MAX_VEC_COMPONENTS];
fs_reg result = prepare_alu_destination_and_sources(bld, instr, op, need_dest);
+#ifndef NDEBUG
+ /* Everything except raw moves, some type conversions, iabs, and ineg
+ * should have 8-bit sources lowered by nir_lower_bit_size in
+ * brw_preprocess_nir or by brw_nir_lower_conversions in
+ * brw_postprocess_nir.
+ */
+ switch (instr->op) {
+ case nir_op_mov:
+ case nir_op_vec2:
+ case nir_op_vec3:
+ case nir_op_vec4:
+ case nir_op_vec8:
+ case nir_op_vec16:
+ case nir_op_i2f16:
+ case nir_op_i2f32:
+ case nir_op_i2i16:
+ case nir_op_i2i32:
+ case nir_op_u2f16:
+ case nir_op_u2f32:
+ case nir_op_u2u16:
+ case nir_op_u2u32:
+ case nir_op_iabs:
+ case nir_op_ineg:
+ break;
+
+ default:
+ for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++) {
+ assert((devinfo->ver == 8 || devinfo->ver == 9) ||
+ type_sz(op[i].type) > 1);
+ }
+ }
+#endif
+
switch (instr->op) {
case nir_op_mov:
case nir_op_vec2:
diff --git a/src/intel/compiler/brw_nir.c b/src/intel/compiler/brw_nir.c
index a50a76e73aa..6b973269835 100644
--- a/src/intel/compiler/brw_nir.c
+++ b/src/intel/compiler/brw_nir.c
@@ -645,6 +645,11 @@ lower_bit_size_callback(const nir_instr *instr, UNUSED void *data)
if (alu->dest.dest.ssa.bit_size >= 32)
return 0;
+ /* Note: nir_op_iabs and nir_op_ineg are not lowered here because the
+ * 8-bit ABS or NEG instruction should eventually get copy propagated
+ * into the MOV that does the type conversion. This results in far
+ * fewer MOV instructions.
+ */
switch (alu->op) {
case nir_op_idiv:
case nir_op_imod:
@@ -666,6 +671,9 @@ lower_bit_size_callback(const nir_instr *instr, UNUSED void *data)
case nir_op_fsin:
case nir_op_fcos:
return devinfo->ver < 9 ? 32 : 0;
+ case nir_op_isign:
+ assert(!"Should have been lowered by nir_opt_algebraic.");
+ return 0;
default:
if (devinfo->ver >= 11) {
if (nir_op_infos[alu->op].num_inputs >= 2 &&
diff --git a/src/intel/compiler/brw_vec4_nir.cpp b/src/intel/compiler/brw_vec4_nir.cpp
index 9cf4a7c8eb5..523cd394c52 100644
--- a/src/intel/compiler/brw_vec4_nir.cpp
+++ b/src/intel/compiler/brw_vec4_nir.cpp
@@ -1145,6 +1145,14 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr)
op[i].swizzle = brw_swizzle_for_nir_swizzle(instr->src[i].swizzle);
}
+#ifndef NDEBUG
+ /* On Gen7 and earlier, no functionality is exposed that should allow 8-bit
+ * integer types to ever exist.
+ */
+ for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
+ assert(type_sz(op[i].type) > 1);
+#endif
+
switch (instr->op) {
case nir_op_mov:
try_immediate_source(instr, &op[0], true);
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