Mesa (main): freedreno: rename Z_TEST_ENABLE->Z_READ_ENABLE, Z_ENABLE->Z_TEST_ENABLE
GitLab Mirror
gitlab-mirror at kemper.freedesktop.org
Thu Aug 19 13:33:26 UTC 2021
Module: Mesa
Branch: main
Commit: 7faee1430a876afba64a6bf837c99d9a1fb25986
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=7faee1430a876afba64a6bf837c99d9a1fb25986
Author: Danylo Piliaiev <dpiliaiev at igalia.com>
Date: Tue Aug 17 18:19:06 2021 +0300
freedreno: rename Z_TEST_ENABLE->Z_READ_ENABLE, Z_ENABLE->Z_TEST_ENABLE
This makes their interaction with Z_BOUNDS_ENABLE more understandable.
Signed-off-by: Danylo Piliaiev <dpiliaiev at igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12407>
---
.../.gitlab-ci/reference/es2gears-a320.log | 8 ++---
.../.gitlab-ci/reference/glxgears-a420.log | 40 +++++++++++-----------
src/freedreno/decode/scripts/parse-submits.lua | 2 +-
src/freedreno/decode/scripts/test.lua | 2 +-
src/freedreno/registers/adreno/a3xx.xml | 6 ++--
src/freedreno/registers/adreno/a4xx.xml | 6 ++--
src/freedreno/registers/adreno/a5xx.xml | 6 ++--
src/freedreno/registers/adreno/a6xx.xml | 6 ++--
src/freedreno/vulkan/tu_clear_blit.c | 2 +-
src/freedreno/vulkan/tu_cmd_buffer.c | 14 ++++----
src/freedreno/vulkan/tu_pipeline.c | 10 +++---
src/gallium/drivers/freedreno/a3xx/fd3_gmem.c | 2 +-
src/gallium/drivers/freedreno/a3xx/fd3_zsa.c | 2 +-
src/gallium/drivers/freedreno/a4xx/fd4_gmem.c | 2 +-
src/gallium/drivers/freedreno/a4xx/fd4_zsa.c | 2 +-
src/gallium/drivers/freedreno/a5xx/fd5_zsa.c | 2 +-
src/gallium/drivers/freedreno/a6xx/fd6_zsa.c | 2 +-
17 files changed, 57 insertions(+), 57 deletions(-)
diff --git a/src/freedreno/.gitlab-ci/reference/es2gears-a320.log b/src/freedreno/.gitlab-ci/reference/es2gears-a320.log
index c174cc74252..f40871704ff 100644
--- a/src/freedreno/.gitlab-ci/reference/es2gears-a320.log
+++ b/src/freedreno/.gitlab-ci/reference/es2gears-a320.log
@@ -267,7 +267,7 @@ t3 opcode: CP_REG_RMW (21) (4 dwords)
rmw (RB_RENDER_CONTROL & 0x00002ff0) | 0x00000000)
118423a8: 0000: c0022100 000020c1 00002ff0 00000000
t0 write RB_DEPTH_CONTROL (2100)
- RB_DEPTH_CONTROL: { Z_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_ALWAYS }
+ RB_DEPTH_CONTROL: { Z_TEST_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_ALWAYS }
118423b8: 0000: 00002100 00000076
t0 write GRAS_CL_VPORT_ZOFFSET (204c)
GRAS_CL_VPORT_ZOFFSET: 0.000000
@@ -536,7 +536,7 @@ t3 opcode: CP_DRAW_INDX (22) (4 dwords)
+ 00000000 RB_BLEND_GREEN: { UINT = 0 | FLOAT = 0.000000 }
+ 00000000 RB_BLEND_BLUE: { UINT = 0 | FLOAT = 0.000000 }
!+ 3c0000ff RB_BLEND_ALPHA: { UINT = 0xff | FLOAT = 1.000000 }
-!+ 00000076 RB_DEPTH_CONTROL: { Z_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_ALWAYS }
+!+ 00000076 RB_DEPTH_CONTROL: { Z_TEST_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_ALWAYS }
!+ 00020000 RB_DEPTH_INFO: { DEPTH_FORMAT = DEPTHX_16 | DEPTH_BASE = 0x40000 }
!+ 00000028 RB_DEPTH_PITCH: 320
+ 00000000 RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP }
@@ -628,7 +628,7 @@ t0 write RB_ALPHA_REF (20c3)
RB_ALPHA_REF: { UINT = 0 | FLOAT = 0.000000 }
118425c0: 0000: 000020c3 00000000
t0 write RB_DEPTH_CONTROL (2100)
- RB_DEPTH_CONTROL: { Z_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_LESS | Z_TEST_ENABLE }
+ RB_DEPTH_CONTROL: { Z_TEST_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_LESS | Z_READ_ENABLE }
118425c8: 0000: 00002100 80000016
t0 write RB_STENCIL_CONTROL (2104)
RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP }
@@ -872,7 +872,7 @@ t3 opcode: CP_DRAW_INDX (22) (4 dwords)
!+ 20000000 RB_MRT[0x2].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO | CLAMP_ENABLE }
!+ 00001c00 RB_MRT[0x3].CONTROL: { ROP_CODE = ROP_COPY | DITHER_MODE = DITHER_ALWAYS | COMPONENT_ENABLE = 0 }
!+ 20000000 RB_MRT[0x3].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO | CLAMP_ENABLE }
-!+ 80000016 RB_DEPTH_CONTROL: { Z_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_LESS | Z_TEST_ENABLE }
+!+ 80000016 RB_DEPTH_CONTROL: { Z_TEST_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_LESS | Z_READ_ENABLE }
+ 00000000 RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP }
+ 00000000 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
+ 00000000 RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
diff --git a/src/freedreno/.gitlab-ci/reference/glxgears-a420.log b/src/freedreno/.gitlab-ci/reference/glxgears-a420.log
index 0b02312d015..91664ba7573 100644
--- a/src/freedreno/.gitlab-ci/reference/glxgears-a420.log
+++ b/src/freedreno/.gitlab-ci/reference/glxgears-a420.log
@@ -270,7 +270,7 @@ t0 write RB_STENCILREFMASK (210b)
RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
109ce024: 0000: 0001210b 00000000 00000000
t0 write RB_DEPTH_CONTROL (2101)
- RB_DEPTH_CONTROL: { Z_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_ALWAYS | Z_TEST_ENABLE }
+ RB_DEPTH_CONTROL: { Z_TEST_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_ALWAYS | Z_READ_ENABLE }
109ce030: 0000: 00002101 80000076
t0 write GRAS_ALPHA_CONTROL (2073)
GRAS_ALPHA_CONTROL: { 0 }
@@ -686,7 +686,7 @@ t3 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords)
!+ ffff0100 RB_FS_OUTPUT: { ENABLE_BLEND = 0 | INDEPENDENT_BLEND | SAMPLE_MASK = 0xffff }
!+ 0000000f RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 }
!+ 00000001 RB_FS_OUTPUT_REG: { MRT = 1 }
-!+ 80000076 RB_DEPTH_CONTROL: { Z_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_ALWAYS | Z_TEST_ENABLE }
+!+ 80000076 RB_DEPTH_CONTROL: { Z_TEST_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_ALWAYS | Z_READ_ENABLE }
!+ 00064002 RB_DEPTH_INFO: { DEPTH_FORMAT = DEPTH4_24_8 | DEPTH_BASE = 0x64000 }
!+ 00000028 RB_DEPTH_PITCH: 1280
!+ 00000028 RB_DEPTH_PITCH2: 1280
@@ -808,7 +808,7 @@ t0 write RB_STENCILREFMASK (210b)
RB_STENCILREFMASK_BF: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
109ce490: 0000: 0001210b 00000000 00000000
t0 write RB_DEPTH_CONTROL (2101)
- RB_DEPTH_CONTROL: { Z_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_LESS | Z_TEST_ENABLE }
+ RB_DEPTH_CONTROL: { Z_TEST_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_LESS | Z_READ_ENABLE }
109ce49c: 0000: 00002101 80000016
t0 write GRAS_ALPHA_CONTROL (2073)
GRAS_ALPHA_CONTROL: { 0 }
@@ -1229,7 +1229,7 @@ t3 opcode: CP_DRAW_INDX_OFFSET (38) (7 dwords)
+ 00000000 RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_NEVER }
!+ ffff0000 RB_FS_OUTPUT: { ENABLE_BLEND = 0 | SAMPLE_MASK = 0xffff }
+ 00000001 RB_FS_OUTPUT_REG: { MRT = 1 }
-!+ 80000016 RB_DEPTH_CONTROL: { Z_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_LESS | Z_TEST_ENABLE }
+!+ 80000016 RB_DEPTH_CONTROL: { Z_TEST_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_LESS | Z_READ_ENABLE }
+ 00000000 RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP }
+ 00000000 RB_STENCIL_CONTROL2: { 0 }
+ 00000000 RB_STENCILREFMASK: { STENCILREF = 0 | STENCILMASK = 0 | STENCILWRITEMASK = 0 }
@@ -1464,7 +1464,7 @@ t0 write CP_SCRATCH[0x5].REG (057d)
:0,31,115,27
109cecc4: 0000: 0000057d 0000001f
t0 write RB_DEPTH_CONTROL (2101)
- RB_DEPTH_CONTROL: { Z_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_LESS | Z_TEST_ENABLE }
+ RB_DEPTH_CONTROL: { Z_TEST_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_LESS | Z_READ_ENABLE }
109ceccc: 0000: 00002101 80000016
t0 write GRAS_ALPHA_CONTROL (2073)
GRAS_ALPHA_CONTROL: { 0 }
@@ -1773,7 +1773,7 @@ t3 opcode: CP_DRAW_INDX_OFFSET (38) (7 dwords)
+ 00000000 GRAS_ALPHA_CONTROL: { 0 }
+ 00000000 RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 }
+ 00000001 RB_FS_OUTPUT_REG: { MRT = 1 }
- + 80000016 RB_DEPTH_CONTROL: { Z_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_LESS | Z_TEST_ENABLE }
+ + 80000016 RB_DEPTH_CONTROL: { Z_TEST_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_LESS | Z_READ_ENABLE }
+ 42001004 VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | ENABLE | 0x40000000 }
+ 00040400 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 }
+ 00000055 VPC_VARYING_INTERP[0].MODE: 0x55
@@ -1860,7 +1860,7 @@ t0 write CP_SCRATCH[0x5].REG (057d)
:0,37,115,33
109cf258: 0000: 0000057d 00000025
t0 write RB_DEPTH_CONTROL (2101)
- RB_DEPTH_CONTROL: { Z_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_LESS | Z_TEST_ENABLE }
+ RB_DEPTH_CONTROL: { Z_TEST_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_LESS | Z_READ_ENABLE }
109cf260: 0000: 00002101 80000016
t0 write GRAS_ALPHA_CONTROL (2073)
GRAS_ALPHA_CONTROL: { 0 }
@@ -2161,7 +2161,7 @@ t3 opcode: CP_DRAW_INDX_OFFSET (38) (7 dwords)
+ 00000000 GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
!+ 00001000 RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 | IJ_PERSP_PIXEL }
+ 00000001 RB_FS_OUTPUT_REG: { MRT = 1 }
- + 80000016 RB_DEPTH_CONTROL: { Z_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_LESS | Z_TEST_ENABLE }
+ + 80000016 RB_DEPTH_CONTROL: { Z_TEST_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_LESS | Z_READ_ENABLE }
+ 00000000 RB_VPORT_Z_CLAMP[0].MIN: 0
+ 00ffffff RB_VPORT_Z_CLAMP[0].MAX: 0xffffff
+ 42001004 VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | ENABLE | 0x40000000 }
@@ -2235,7 +2235,7 @@ t0 write CP_SCRATCH[0x5].REG (057d)
:0,43,115,39
109cf7b8: 0000: 0000057d 0000002b
t0 write RB_DEPTH_CONTROL (2101)
- RB_DEPTH_CONTROL: { Z_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_LESS | Z_TEST_ENABLE }
+ RB_DEPTH_CONTROL: { Z_TEST_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_LESS | Z_READ_ENABLE }
109cf7c0: 0000: 00002101 80000016
t0 write GRAS_ALPHA_CONTROL (2073)
GRAS_ALPHA_CONTROL: { 0 }
@@ -2573,7 +2573,7 @@ t3 opcode: CP_DRAW_INDX_OFFSET (38) (7 dwords)
+ 00000000 GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
!+ 00000000 RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 }
+ 00000001 RB_FS_OUTPUT_REG: { MRT = 1 }
- + 80000016 RB_DEPTH_CONTROL: { Z_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_LESS | Z_TEST_ENABLE }
+ + 80000016 RB_DEPTH_CONTROL: { Z_TEST_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_LESS | Z_READ_ENABLE }
+ 00000000 RB_VPORT_Z_CLAMP[0].MIN: 0
+ 00ffffff RB_VPORT_Z_CLAMP[0].MAX: 0xffffff
+ 42001004 VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | ENABLE | 0x40000000 }
@@ -2804,7 +2804,7 @@ t0 write CP_SCRATCH[0x5].REG (057d)
:0,67,115,63
109cff44: 0000: 0000057d 00000043
t0 write RB_DEPTH_CONTROL (2101)
- RB_DEPTH_CONTROL: { Z_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_LESS | Z_TEST_ENABLE }
+ RB_DEPTH_CONTROL: { Z_TEST_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_LESS | Z_READ_ENABLE }
109cff4c: 0000: 00002101 80000016
t0 write GRAS_ALPHA_CONTROL (2073)
GRAS_ALPHA_CONTROL: { 0 }
@@ -3113,7 +3113,7 @@ t3 opcode: CP_DRAW_INDX_OFFSET (38) (7 dwords)
+ 00000000 GRAS_ALPHA_CONTROL: { 0 }
+ 00000000 RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 }
+ 00000001 RB_FS_OUTPUT_REG: { MRT = 1 }
- + 80000016 RB_DEPTH_CONTROL: { Z_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_LESS | Z_TEST_ENABLE }
+ + 80000016 RB_DEPTH_CONTROL: { Z_TEST_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_LESS | Z_READ_ENABLE }
+ 42001004 VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | ENABLE | 0x40000000 }
+ 00040400 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 }
+ 00000055 VPC_VARYING_INTERP[0].MODE: 0x55
@@ -3200,7 +3200,7 @@ t0 write CP_SCRATCH[0x5].REG (057d)
:0,73,115,69
109d04d8: 0000: 0000057d 00000049
t0 write RB_DEPTH_CONTROL (2101)
- RB_DEPTH_CONTROL: { Z_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_LESS | Z_TEST_ENABLE }
+ RB_DEPTH_CONTROL: { Z_TEST_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_LESS | Z_READ_ENABLE }
109d04e0: 0000: 00002101 80000016
t0 write GRAS_ALPHA_CONTROL (2073)
GRAS_ALPHA_CONTROL: { 0 }
@@ -3501,7 +3501,7 @@ t3 opcode: CP_DRAW_INDX_OFFSET (38) (7 dwords)
+ 00000000 GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
!+ 00001000 RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 | IJ_PERSP_PIXEL }
+ 00000001 RB_FS_OUTPUT_REG: { MRT = 1 }
- + 80000016 RB_DEPTH_CONTROL: { Z_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_LESS | Z_TEST_ENABLE }
+ + 80000016 RB_DEPTH_CONTROL: { Z_TEST_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_LESS | Z_READ_ENABLE }
+ 00000000 RB_VPORT_Z_CLAMP[0].MIN: 0
+ 00ffffff RB_VPORT_Z_CLAMP[0].MAX: 0xffffff
+ 42001004 VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | ENABLE | 0x40000000 }
@@ -3575,7 +3575,7 @@ t0 write CP_SCRATCH[0x5].REG (057d)
:0,79,115,75
109d0a38: 0000: 0000057d 0000004f
t0 write RB_DEPTH_CONTROL (2101)
- RB_DEPTH_CONTROL: { Z_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_LESS | Z_TEST_ENABLE }
+ RB_DEPTH_CONTROL: { Z_TEST_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_LESS | Z_READ_ENABLE }
109d0a40: 0000: 00002101 80000016
t0 write GRAS_ALPHA_CONTROL (2073)
GRAS_ALPHA_CONTROL: { 0 }
@@ -3913,7 +3913,7 @@ t3 opcode: CP_DRAW_INDX_OFFSET (38) (7 dwords)
+ 00000000 GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
!+ 00000000 RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 }
+ 00000001 RB_FS_OUTPUT_REG: { MRT = 1 }
- + 80000016 RB_DEPTH_CONTROL: { Z_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_LESS | Z_TEST_ENABLE }
+ + 80000016 RB_DEPTH_CONTROL: { Z_TEST_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_LESS | Z_READ_ENABLE }
+ 00000000 RB_VPORT_Z_CLAMP[0].MIN: 0
+ 00ffffff RB_VPORT_Z_CLAMP[0].MAX: 0xffffff
+ 42001004 VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | ENABLE | 0x40000000 }
@@ -4144,7 +4144,7 @@ t0 write CP_SCRATCH[0x5].REG (057d)
:0,103,115,99
109d11c4: 0000: 0000057d 00000067
t0 write RB_DEPTH_CONTROL (2101)
- RB_DEPTH_CONTROL: { Z_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_LESS | Z_TEST_ENABLE }
+ RB_DEPTH_CONTROL: { Z_TEST_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_LESS | Z_READ_ENABLE }
109d11cc: 0000: 00002101 80000016
t0 write GRAS_ALPHA_CONTROL (2073)
GRAS_ALPHA_CONTROL: { 0 }
@@ -4453,7 +4453,7 @@ t3 opcode: CP_DRAW_INDX_OFFSET (38) (7 dwords)
+ 00000000 GRAS_ALPHA_CONTROL: { 0 }
+ 00000000 RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 }
+ 00000001 RB_FS_OUTPUT_REG: { MRT = 1 }
- + 80000016 RB_DEPTH_CONTROL: { Z_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_LESS | Z_TEST_ENABLE }
+ + 80000016 RB_DEPTH_CONTROL: { Z_TEST_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_LESS | Z_READ_ENABLE }
+ 42001004 VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | ENABLE | 0x40000000 }
+ 00040400 VPC_PACK: { NUMBYPASSVAR = 0 | NUMFPNONPOSVAR = 4 | NUMNONPOSVSVAR = 4 }
+ 00000055 VPC_VARYING_INTERP[0].MODE: 0x55
@@ -4540,7 +4540,7 @@ t0 write CP_SCRATCH[0x5].REG (057d)
:0,109,115,105
109d1758: 0000: 0000057d 0000006d
t0 write RB_DEPTH_CONTROL (2101)
- RB_DEPTH_CONTROL: { Z_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_LESS | Z_TEST_ENABLE }
+ RB_DEPTH_CONTROL: { Z_TEST_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_LESS | Z_READ_ENABLE }
109d1760: 0000: 00002101 80000016
t0 write GRAS_ALPHA_CONTROL (2073)
GRAS_ALPHA_CONTROL: { 0 }
@@ -4841,7 +4841,7 @@ t3 opcode: CP_DRAW_INDX_OFFSET (38) (7 dwords)
+ 00000000 GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
!+ 00001000 RB_RENDER_CONTROL2: { COORD_MASK = 0 | MSAA_SAMPLES = 0 | IJ_PERSP_PIXEL }
+ 00000001 RB_FS_OUTPUT_REG: { MRT = 1 }
- + 80000016 RB_DEPTH_CONTROL: { Z_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_LESS | Z_TEST_ENABLE }
+ + 80000016 RB_DEPTH_CONTROL: { Z_TEST_ENABLE | Z_WRITE_ENABLE | ZFUNC = FUNC_LESS | Z_READ_ENABLE }
+ 00000000 RB_VPORT_Z_CLAMP[0].MIN: 0
+ 00ffffff RB_VPORT_Z_CLAMP[0].MAX: 0xffffff
+ 42001004 VPC_ATTR: { TOTALATTR = 4 | THRDASSIGN = 1 | ENABLE | 0x40000000 }
diff --git a/src/freedreno/decode/scripts/parse-submits.lua b/src/freedreno/decode/scripts/parse-submits.lua
index 1e10c6008b2..96fa66957dd 100644
--- a/src/freedreno/decode/scripts/parse-submits.lua
+++ b/src/freedreno/decode/scripts/parse-submits.lua
@@ -386,7 +386,7 @@ function draw(primtype, nindx)
depthwrite = true
end
- if r.RB_DEPTH_CNTL.Z_ENABLE then
+ if r.RB_DEPTH_CNTL.Z_TEST_ENABLE then
depthtest = true
end
diff --git a/src/freedreno/decode/scripts/test.lua b/src/freedreno/decode/scripts/test.lua
index e9d8db2b6ae..86890d6a069 100644
--- a/src/freedreno/decode/scripts/test.lua
+++ b/src/freedreno/decode/scripts/test.lua
@@ -11,7 +11,7 @@ function draw(primtype, nindx)
-- io.write("GRAS_CL_VPORT_XOFFSET: " .. r.GRAS_CL_VPORT_XOFFSET .. "\n")
io.write("RB_MRT[0].CONTROL.ROP_CODE: " .. r.RB_MRT[0].CONTROL.ROP_CODE .. "\n")
io.write("SP_VS_OUT[0].A_COMPMASK: " .. r.SP_VS_OUT[0].A_COMPMASK .. "\n")
- --io.write("RB_DEPTH_CONTROL.Z_ENABLE: " .. tostring(r.RB_DEPTH_CONTROL.Z_ENABLE) .. "\n")
+ --io.write("RB_DEPTH_CONTROL.Z_TEST_ENABLE: " .. tostring(r.RB_DEPTH_CONTROL.Z_TEST_ENABLE) .. "\n")
io.write("0x2280: written=" .. regs.written(0x2280) .. ", lastval=" .. regs.lastval(0x2280) .. ", val=" .. regs.val(0x2280) .. "\n")
end
diff --git a/src/freedreno/registers/adreno/a3xx.xml b/src/freedreno/registers/adreno/a3xx.xml
index 0819dc4ede7..733752b6823 100644
--- a/src/freedreno/registers/adreno/a3xx.xml
+++ b/src/freedreno/registers/adreno/a3xx.xml
@@ -972,13 +972,13 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
moved out into RB_STENCIL_CONTROL?
-->
<bitfield name="FRAG_WRITES_Z" pos="0" type="boolean"/>
- <bitfield name="Z_ENABLE" pos="1" type="boolean"/>
+ <bitfield name="Z_TEST_ENABLE" pos="1" type="boolean"/>
<bitfield name="Z_WRITE_ENABLE" pos="2" type="boolean"/>
<bitfield name="EARLY_Z_DISABLE" pos="3" type="boolean"/>
<bitfield name="ZFUNC" low="4" high="6" type="adreno_compare_func"/>
<bitfield name="Z_CLAMP_ENABLE" pos="7" type="boolean"/>
- <doc>Z_TEST_ENABLE bit is set for zfunc other than GL_ALWAYS or GL_NEVER</doc>
- <bitfield name="Z_TEST_ENABLE" pos="31" type="boolean"/>
+ <doc>Z_READ_ENABLE bit is set for zfunc other than GL_ALWAYS or GL_NEVER</doc>
+ <bitfield name="Z_READ_ENABLE" pos="31" type="boolean"/>
</reg32>
<reg32 offset="0x2101" name="RB_DEPTH_CLEAR">
<doc>seems to be always set to 0x00000000</doc>
diff --git a/src/freedreno/registers/adreno/a4xx.xml b/src/freedreno/registers/adreno/a4xx.xml
index 94c795cec78..3f0e1ae0e4a 100644
--- a/src/freedreno/registers/adreno/a4xx.xml
+++ b/src/freedreno/registers/adreno/a4xx.xml
@@ -1052,14 +1052,14 @@ perhaps they should be taken with a grain of salt
moved out into RB_STENCIL_CONTROL?
-->
<bitfield name="FRAG_WRITES_Z" pos="0" type="boolean"/>
- <bitfield name="Z_ENABLE" pos="1" type="boolean"/>
+ <bitfield name="Z_TEST_ENABLE" pos="1" type="boolean"/>
<bitfield name="Z_WRITE_ENABLE" pos="2" type="boolean"/>
<bitfield name="ZFUNC" low="4" high="6" type="adreno_compare_func"/>
<bitfield name="Z_CLAMP_ENABLE" pos="7" type="boolean"/>
<bitfield name="EARLY_Z_DISABLE" pos="16" type="boolean"/>
<bitfield name="FORCE_FRAGZ_TO_FS" pos="17" type="boolean"/>
- <doc>Z_TEST_ENABLE bit is set for zfunc other than GL_ALWAYS or GL_NEVER</doc>
- <bitfield name="Z_TEST_ENABLE" pos="31" type="boolean"/>
+ <doc>Z_READ_ENABLE bit is set for zfunc other than GL_ALWAYS or GL_NEVER</doc>
+ <bitfield name="Z_READ_ENABLE" pos="31" type="boolean"/>
</reg32>
<reg32 offset="0x2102" name="RB_DEPTH_CLEAR"/>
<reg32 offset="0x2103" name="RB_DEPTH_INFO">
diff --git a/src/freedreno/registers/adreno/a5xx.xml b/src/freedreno/registers/adreno/a5xx.xml
index a2a3c71364b..55e90f29b68 100644
--- a/src/freedreno/registers/adreno/a5xx.xml
+++ b/src/freedreno/registers/adreno/a5xx.xml
@@ -2088,11 +2088,11 @@ bit 7 for RECTLIST (clear) when z32s8 (used for clear of depth32? not set
<bitfield name="UNK1" pos="1" type="boolean"/>
</reg32>
<reg32 offset="0xe1b1" name="RB_DEPTH_CNTL">
- <bitfield name="Z_ENABLE" pos="0" type="boolean"/>
+ <bitfield name="Z_TEST_ENABLE" pos="0" type="boolean"/>
<bitfield name="Z_WRITE_ENABLE" pos="1" type="boolean"/>
<bitfield name="ZFUNC" low="2" high="4" type="adreno_compare_func"/>
- <doc>Z_TEST_ENABLE bit is set for zfunc other than GL_ALWAYS or GL_NEVER</doc>
- <bitfield name="Z_TEST_ENABLE" pos="6" type="boolean"/>
+ <doc>Z_READ_ENABLE bit is set for zfunc other than GL_ALWAYS or GL_NEVER</doc>
+ <bitfield name="Z_READ_ENABLE" pos="6" type="boolean"/>
</reg32>
<reg32 offset="0xe1b2" name="RB_DEPTH_BUFFER_INFO">
<bitfield name="DEPTH_FORMAT" low="0" high="2" type="a5xx_depth_format"/>
diff --git a/src/freedreno/registers/adreno/a6xx.xml b/src/freedreno/registers/adreno/a6xx.xml
index b0bb6adff06..92b93740c77 100644
--- a/src/freedreno/registers/adreno/a6xx.xml
+++ b/src/freedreno/registers/adreno/a6xx.xml
@@ -2099,15 +2099,15 @@ to upconvert to 32b float internally?
</reg32>
<reg32 offset="0x8871" name="RB_DEPTH_CNTL">
- <bitfield name="Z_ENABLE" pos="0" type="boolean"/>
+ <bitfield name="Z_TEST_ENABLE" pos="0" type="boolean"/>
<bitfield name="Z_WRITE_ENABLE" pos="1" type="boolean"/>
<bitfield name="ZFUNC" low="2" high="4" type="adreno_compare_func"/>
<bitfield name="Z_CLAMP_ENABLE" pos="5" type="boolean"/>
<doc>
- Z_TEST_ENABLE bit is set for zfunc other than GL_ALWAYS or GL_NEVER
+ Z_READ_ENABLE bit is set for zfunc other than GL_ALWAYS or GL_NEVER
also set when Z_BOUNDS_ENABLE is set
</doc>
- <bitfield name="Z_TEST_ENABLE" pos="6" type="boolean"/>
+ <bitfield name="Z_READ_ENABLE" pos="6" type="boolean"/>
<bitfield name="Z_BOUNDS_ENABLE" pos="7" type="boolean"/>
</reg32>
<!-- duplicates GRAS_SU_DEPTH_BUFFER_INFO: -->
diff --git a/src/freedreno/vulkan/tu_clear_blit.c b/src/freedreno/vulkan/tu_clear_blit.c
index 130720a53bc..5f80034e89e 100644
--- a/src/freedreno/vulkan/tu_clear_blit.c
+++ b/src/freedreno/vulkan/tu_clear_blit.c
@@ -2263,7 +2263,7 @@ tu_clear_sysmem_attachments(struct tu_cmd_buffer *cmd,
tu_cs_emit_regs(cs, A6XX_RB_DEPTH_PLANE_CNTL());
tu_cs_emit_regs(cs, A6XX_RB_DEPTH_CNTL(
- .z_enable = z_clear,
+ .z_test_enable = z_clear,
.z_write_enable = z_clear,
.zfunc = FUNC_ALWAYS));
tu_cs_emit_regs(cs, A6XX_GRAS_SU_DEPTH_PLANE_CNTL());
diff --git a/src/freedreno/vulkan/tu_cmd_buffer.c b/src/freedreno/vulkan/tu_cmd_buffer.c
index d5ca6e1d7bb..5903dad7ff8 100644
--- a/src/freedreno/vulkan/tu_cmd_buffer.c
+++ b/src/freedreno/vulkan/tu_cmd_buffer.c
@@ -2386,10 +2386,10 @@ tu_CmdSetDepthTestEnableEXT(VkCommandBuffer commandBuffer,
{
TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
- cmd->state.rb_depth_cntl &= ~A6XX_RB_DEPTH_CNTL_Z_ENABLE;
+ cmd->state.rb_depth_cntl &= ~A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE;
if (depthTestEnable)
- cmd->state.rb_depth_cntl |= A6XX_RB_DEPTH_CNTL_Z_ENABLE;
+ cmd->state.rb_depth_cntl |= A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE;
cmd->state.dirty |= TU_CMD_DIRTY_RB_DEPTH_CNTL;
}
@@ -3517,9 +3517,9 @@ tu6_calculate_lrz_state(struct tu_cmd_buffer *cmd,
bool force_disable_write = pipeline->lrz.force_disable_mask & TU_LRZ_FORCE_DISABLE_WRITE;
enum tu_lrz_direction lrz_direction = TU_LRZ_UNKNOWN;
- gras_lrz_cntl.enable = cmd->state.rb_depth_cntl & A6XX_RB_DEPTH_CNTL_Z_ENABLE;
+ gras_lrz_cntl.enable = cmd->state.rb_depth_cntl & A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE;
gras_lrz_cntl.lrz_write = cmd->state.rb_depth_cntl & A6XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE;
- gras_lrz_cntl.z_test_enable = cmd->state.rb_depth_cntl & A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE;
+ gras_lrz_cntl.z_test_enable = cmd->state.rb_depth_cntl & A6XX_RB_DEPTH_CNTL_Z_READ_ENABLE;
gras_lrz_cntl.z_bounds_enable = cmd->state.rb_depth_cntl & A6XX_RB_DEPTH_CNTL_Z_BOUNDS_ENABLE;
VkCompareOp depth_compare_op = (cmd->state.rb_depth_cntl & A6XX_RB_DEPTH_CNTL_ZFUNC__MASK) >> A6XX_RB_DEPTH_CNTL_ZFUNC__SHIFT;
@@ -3659,7 +3659,7 @@ tu6_build_depth_plane_z_mode(struct tu_cmd_buffer *cmd)
struct tu_draw_state ds = tu_cs_draw_state(&cmd->sub_cs, &cs, 4);
enum a6xx_ztest_mode zmode = A6XX_EARLY_Z;
- bool depth_test_enable = cmd->state.rb_depth_cntl & A6XX_RB_DEPTH_CNTL_Z_ENABLE;
+ bool depth_test_enable = cmd->state.rb_depth_cntl & A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE;
bool depth_write = tu6_writes_depth(cmd, depth_test_enable);
bool stencil_write = tu6_writes_stencil(cmd);
@@ -3739,9 +3739,9 @@ tu6_draw_common(struct tu_cmd_buffer *cmd,
struct tu_cs cs = tu_cmd_dynamic_state(cmd, TU_DYNAMIC_STATE_RB_DEPTH_CNTL, 2);
uint32_t rb_depth_cntl = cmd->state.rb_depth_cntl;
- if ((rb_depth_cntl & A6XX_RB_DEPTH_CNTL_Z_ENABLE) ||
+ if ((rb_depth_cntl & A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE) ||
(rb_depth_cntl & A6XX_RB_DEPTH_CNTL_Z_BOUNDS_ENABLE))
- rb_depth_cntl |= A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE;
+ rb_depth_cntl |= A6XX_RB_DEPTH_CNTL_Z_READ_ENABLE;
if (pipeline->rb_depth_cntl_disable)
rb_depth_cntl = 0;
diff --git a/src/freedreno/vulkan/tu_pipeline.c b/src/freedreno/vulkan/tu_pipeline.c
index 6c9ca2458ac..12a9e3ee88f 100644
--- a/src/freedreno/vulkan/tu_pipeline.c
+++ b/src/freedreno/vulkan/tu_pipeline.c
@@ -2480,7 +2480,7 @@ tu_pipeline_builder_parse_dynamic(struct tu_pipeline_builder *builder,
break;
case VK_DYNAMIC_STATE_DEPTH_TEST_ENABLE_EXT:
pipeline->rb_depth_cntl_mask &=
- ~(A6XX_RB_DEPTH_CNTL_Z_ENABLE | A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE);
+ ~(A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE | A6XX_RB_DEPTH_CNTL_Z_READ_ENABLE);
pipeline->dynamic_state_mask |= BIT(TU_DYNAMIC_STATE_RB_DEPTH_CNTL);
break;
case VK_DYNAMIC_STATE_DEPTH_WRITE_ENABLE_EXT:
@@ -2493,7 +2493,7 @@ tu_pipeline_builder_parse_dynamic(struct tu_pipeline_builder *builder,
break;
case VK_DYNAMIC_STATE_DEPTH_BOUNDS_TEST_ENABLE_EXT:
pipeline->rb_depth_cntl_mask &=
- ~(A6XX_RB_DEPTH_CNTL_Z_BOUNDS_ENABLE | A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE);
+ ~(A6XX_RB_DEPTH_CNTL_Z_BOUNDS_ENABLE | A6XX_RB_DEPTH_CNTL_Z_READ_ENABLE);
pipeline->dynamic_state_mask |= BIT(TU_DYNAMIC_STATE_RB_DEPTH_CNTL);
break;
case VK_DYNAMIC_STATE_STENCIL_TEST_ENABLE_EXT:
@@ -2793,9 +2793,9 @@ tu_pipeline_builder_parse_depth_stencil(struct tu_pipeline_builder *builder,
builder->depth_attachment_format != VK_FORMAT_S8_UINT) {
if (ds_info->depthTestEnable) {
rb_depth_cntl |=
- A6XX_RB_DEPTH_CNTL_Z_ENABLE |
+ A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE |
A6XX_RB_DEPTH_CNTL_ZFUNC(tu6_compare_func(ds_info->depthCompareOp)) |
- A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE; /* TODO: don't set for ALWAYS/NEVER */
+ A6XX_RB_DEPTH_CNTL_Z_READ_ENABLE; /* TODO: don't set for ALWAYS/NEVER */
if (rast_info->depthClampEnable)
rb_depth_cntl |= A6XX_RB_DEPTH_CNTL_Z_CLAMP_ENABLE;
@@ -2805,7 +2805,7 @@ tu_pipeline_builder_parse_depth_stencil(struct tu_pipeline_builder *builder,
}
if (ds_info->depthBoundsTestEnable)
- rb_depth_cntl |= A6XX_RB_DEPTH_CNTL_Z_BOUNDS_ENABLE | A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE;
+ rb_depth_cntl |= A6XX_RB_DEPTH_CNTL_Z_BOUNDS_ENABLE | A6XX_RB_DEPTH_CNTL_Z_READ_ENABLE;
} else {
/* if RB_DEPTH_CNTL is set dynamically, we need to make sure it is set
* to 0 when this pipeline is used, as enabling depth test when there
diff --git a/src/gallium/drivers/freedreno/a3xx/fd3_gmem.c b/src/gallium/drivers/freedreno/a3xx/fd3_gmem.c
index 114363155f2..e338015fc8f 100644
--- a/src/gallium/drivers/freedreno/a3xx/fd3_gmem.c
+++ b/src/gallium/drivers/freedreno/a3xx/fd3_gmem.c
@@ -524,7 +524,7 @@ emit_mem2gmem_surf(struct fd_batch *batch, const uint32_t bases[],
OUT_PKT0(ring, REG_A3XX_RB_DEPTH_CONTROL, 1);
OUT_RING(ring, (A3XX_RB_DEPTH_CONTROL_FRAG_WRITES_Z |
A3XX_RB_DEPTH_CONTROL_Z_WRITE_ENABLE |
- A3XX_RB_DEPTH_CONTROL_Z_ENABLE |
+ A3XX_RB_DEPTH_CONTROL_Z_TEST_ENABLE |
A3XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE |
A3XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_ALWAYS)));
diff --git a/src/gallium/drivers/freedreno/a3xx/fd3_zsa.c b/src/gallium/drivers/freedreno/a3xx/fd3_zsa.c
index 7cbb287d494..4471af75717 100644
--- a/src/gallium/drivers/freedreno/a3xx/fd3_zsa.c
+++ b/src/gallium/drivers/freedreno/a3xx/fd3_zsa.c
@@ -49,7 +49,7 @@ fd3_zsa_state_create(struct pipe_context *pctx,
if (cso->depth_enabled)
so->rb_depth_control |=
- A3XX_RB_DEPTH_CONTROL_Z_ENABLE | A3XX_RB_DEPTH_CONTROL_Z_TEST_ENABLE;
+ A3XX_RB_DEPTH_CONTROL_Z_TEST_ENABLE | A3XX_RB_DEPTH_CONTROL_Z_READ_ENABLE;
if (cso->depth_writemask)
so->rb_depth_control |= A3XX_RB_DEPTH_CONTROL_Z_WRITE_ENABLE;
diff --git a/src/gallium/drivers/freedreno/a4xx/fd4_gmem.c b/src/gallium/drivers/freedreno/a4xx/fd4_gmem.c
index e139de73bd4..15b7e64cf58 100644
--- a/src/gallium/drivers/freedreno/a4xx/fd4_gmem.c
+++ b/src/gallium/drivers/freedreno/a4xx/fd4_gmem.c
@@ -482,7 +482,7 @@ fd4_emit_tile_mem2gmem(struct fd_batch *batch,
fd4_gmem_emit_set_prog(ctx, &emit, &ctx->blit_zs);
OUT_PKT0(ring, REG_A4XX_RB_DEPTH_CONTROL, 1);
- OUT_RING(ring, A4XX_RB_DEPTH_CONTROL_Z_ENABLE |
+ OUT_RING(ring, A4XX_RB_DEPTH_CONTROL_Z_TEST_ENABLE |
A4XX_RB_DEPTH_CONTROL_Z_WRITE_ENABLE |
A4XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_ALWAYS) |
A4XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE);
diff --git a/src/gallium/drivers/freedreno/a4xx/fd4_zsa.c b/src/gallium/drivers/freedreno/a4xx/fd4_zsa.c
index 07c18d0f375..62d6b4727d1 100644
--- a/src/gallium/drivers/freedreno/a4xx/fd4_zsa.c
+++ b/src/gallium/drivers/freedreno/a4xx/fd4_zsa.c
@@ -49,7 +49,7 @@ fd4_zsa_state_create(struct pipe_context *pctx,
if (cso->depth_enabled)
so->rb_depth_control |=
- A4XX_RB_DEPTH_CONTROL_Z_ENABLE | A4XX_RB_DEPTH_CONTROL_Z_TEST_ENABLE;
+ A4XX_RB_DEPTH_CONTROL_Z_TEST_ENABLE | A4XX_RB_DEPTH_CONTROL_Z_READ_ENABLE;
if (cso->depth_writemask)
so->rb_depth_control |= A4XX_RB_DEPTH_CONTROL_Z_WRITE_ENABLE;
diff --git a/src/gallium/drivers/freedreno/a5xx/fd5_zsa.c b/src/gallium/drivers/freedreno/a5xx/fd5_zsa.c
index 3e08c3b85e8..f541838d8a1 100644
--- a/src/gallium/drivers/freedreno/a5xx/fd5_zsa.c
+++ b/src/gallium/drivers/freedreno/a5xx/fd5_zsa.c
@@ -70,7 +70,7 @@ fd5_zsa_state_create(struct pipe_context *pctx,
if (cso->depth_enabled)
so->rb_depth_cntl |=
- A5XX_RB_DEPTH_CNTL_Z_ENABLE | A5XX_RB_DEPTH_CNTL_Z_TEST_ENABLE;
+ A5XX_RB_DEPTH_CNTL_Z_TEST_ENABLE | A5XX_RB_DEPTH_CNTL_Z_READ_ENABLE;
if (cso->depth_writemask)
so->rb_depth_cntl |= A5XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE;
diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_zsa.c b/src/gallium/drivers/freedreno/a6xx/fd6_zsa.c
index 9c638116895..7354371694c 100644
--- a/src/gallium/drivers/freedreno/a6xx/fd6_zsa.c
+++ b/src/gallium/drivers/freedreno/a6xx/fd6_zsa.c
@@ -108,7 +108,7 @@ fd6_zsa_state_create(struct pipe_context *pctx,
if (cso->depth_enabled) {
so->rb_depth_cntl |=
- A6XX_RB_DEPTH_CNTL_Z_ENABLE | A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE;
+ A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE | A6XX_RB_DEPTH_CNTL_Z_READ_ENABLE;
so->lrz.test = true;
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