Mesa (main): ac/surface: allow arbitrary swizzle modes for displayable DCC

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Module: Mesa
Branch: main
Commit: 556c10c02c0aa8032aef53090671e22500e25745
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=556c10c02c0aa8032aef53090671e22500e25745

Author: Marek Olšák <marek.olsak at amd.com>
Date:   Tue Aug 17 12:57:03 2021 -0400

ac/surface: allow arbitrary swizzle modes for displayable DCC

Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12430>

---

 src/amd/common/ac_surface.c | 10 ----------
 1 file changed, 10 deletions(-)

diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c
index 3bcec29292a..c85f41bcb45 100644
--- a/src/amd/common/ac_surface.c
+++ b/src/amd/common/ac_surface.c
@@ -1426,11 +1426,6 @@ static bool is_dcc_supported_by_DCN(const struct radeon_info *info,
 
    switch (info->chip_class) {
    case GFX9:
-      /* Only support 64KB_S_X, so that we have only 1 variant of the retile shader. */
-      if (info->use_display_dcc_with_retile_blit &&
-          surf->u.gfx9.swizzle_mode != ADDR_SW_64KB_S_X)
-         return false;
-
       /* There are more constraints, but we always set
        * INDEPENDENT_64B_BLOCKS = 1 and MAX_COMPRESSED_BLOCK_SIZE = 64B,
        * which always works.
@@ -1440,11 +1435,6 @@ static bool is_dcc_supported_by_DCN(const struct radeon_info *info,
       return true;
    case GFX10:
    case GFX10_3:
-      /* Only support 64KB_R_X, so that we have only 1 variant of the retile shader. */
-      if (info->use_display_dcc_with_retile_blit &&
-          surf->u.gfx9.swizzle_mode != ADDR_SW_64KB_R_X)
-         return false;
-
       /* DCN requires INDEPENDENT_128B_BLOCKS = 0 only on Navi1x. */
       if (info->chip_class == GFX10 && surf->u.gfx9.color.dcc.independent_128B_blocks)
          return false;