Mesa (main): anv: Optimize genX(cmd_buffer_emit_gfx12_depth_wa)
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Fri Aug 20 18:02:26 UTC 2021
Module: Mesa
Branch: main
Commit: 4003f2d48d9ca0e67d75b6f32005dbbfbdcff06a
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=4003f2d48d9ca0e67d75b6f32005dbbfbdcff06a
Author: Nanley Chery <nanley.g.chery at intel.com>
Date: Wed Jun 16 10:17:38 2021 -0700
anv: Optimize genX(cmd_buffer_emit_gfx12_depth_wa)
Only emit the workaround as needed.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11454>
---
src/intel/vulkan/anv_private.h | 13 +++++++++++++
src/intel/vulkan/genX_cmd_buffer.c | 21 +++++++++++++++++++++
2 files changed, 34 insertions(+)
diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h
index 6186356500c..801c8e8f57f 100644
--- a/src/intel/vulkan/anv_private.h
+++ b/src/intel/vulkan/anv_private.h
@@ -2967,6 +2967,12 @@ struct anv_cmd_graphics_state {
} gfx7;
};
+enum anv_depth_reg_mode {
+ ANV_DEPTH_REG_MODE_UNKNOWN = 0,
+ ANV_DEPTH_REG_MODE_HW_DEFAULT,
+ ANV_DEPTH_REG_MODE_D16,
+};
+
/** State tracking for compute pipeline
*
* This has anv_cmd_pipeline_state as a base struct to track things which get
@@ -3043,6 +3049,13 @@ struct anv_cmd_state {
*/
bool hiz_enabled;
+ /* We ensure the registers for the gfx12 D16 fix are initalized at the
+ * first non-NULL depth stencil packet emission of every command buffer.
+ * For secondary command buffer execution, we transfer the state from the
+ * last command buffer to the primary (if known).
+ */
+ enum anv_depth_reg_mode depth_reg_mode;
+
bool conditional_render_enabled;
/**
diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c
index 5c287f836ed..4c00eb3da2e 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -2004,6 +2004,11 @@ genX(CmdExecuteCommands)(
secondary->perf_query_pool == primary->perf_query_pool);
if (secondary->perf_query_pool)
primary->perf_query_pool = secondary->perf_query_pool;
+
+#if GFX_VERx10 == 120
+ if (secondary->state.depth_reg_mode != ANV_DEPTH_REG_MODE_UNKNOWN)
+ primary->state.depth_reg_mode = secondary->state.depth_reg_mode;
+#endif
}
/* The secondary isn't counted in our VF cache tracking so we need to
@@ -5534,6 +5539,19 @@ genX(cmd_buffer_emit_gfx12_depth_wa)(struct anv_cmd_buffer *cmd_buffer,
#if GFX_VERx10 == 120
const bool fmt_is_d16 = surf->format == ISL_FORMAT_R16_UNORM;
+ switch (cmd_buffer->state.depth_reg_mode) {
+ case ANV_DEPTH_REG_MODE_HW_DEFAULT:
+ if (!fmt_is_d16)
+ return;
+ break;
+ case ANV_DEPTH_REG_MODE_D16:
+ if (fmt_is_d16)
+ return;
+ break;
+ case ANV_DEPTH_REG_MODE_UNKNOWN:
+ break;
+ }
+
/* We'll change some CHICKEN registers depending on the depth surface
* format. Do a depth flush and stall so the pipeline is not using these
* settings while we change the registers.
@@ -5563,6 +5581,9 @@ genX(cmd_buffer_emit_gfx12_depth_wa)(struct anv_cmd_buffer *cmd_buffer,
reg.HZDepthTestLEGEOptimizationDisable = fmt_is_d16;
reg.HZDepthTestLEGEOptimizationDisableMask = true;
}
+
+ cmd_buffer->state.depth_reg_mode =
+ fmt_is_d16 ? ANV_DEPTH_REG_MODE_D16 : ANV_DEPTH_REG_MODE_HW_DEFAULT;
#endif
}
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