Mesa (main): intel/compiler: Add unified barrier support for TCS

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: 6a950bab0cf014d7919be501d54491a06c1dbf0d
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=6a950bab0cf014d7919be501d54491a06c1dbf0d

Author: Jordan Justen <jordan.l.justen at intel.com>
Date:   Wed Sep  2 15:07:02 2020 -0700

intel/compiler: Add unified barrier support for TCS

Program the producers/consumer fields for TCS Barrier messages.
Producer and consumer fields are set to number of TCS threads.

Ref: Bspec 54006 for Barrier Data Payload
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge at intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11963>

---

 src/intel/compiler/brw_fs_nir.cpp | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp
index 58fb065a1dd..ca6c1de1c85 100644
--- a/src/intel/compiler/brw_fs_nir.cpp
+++ b/src/intel/compiler/brw_fs_nir.cpp
@@ -2824,7 +2824,14 @@ fs_visitor::nir_emit_tcs_intrinsic(const fs_builder &bld,
       /* Zero the message header */
       bld.exec_all().MOV(m0, brw_imm_ud(0u));
 
-      if (devinfo->ver >= 11) {
+      if (devinfo->verx10 >= 125) {
+         /* From BSpec: 54006, mov r0.2[31:24] into m0.2[31:24] and m0.2[23:16] */
+         fs_reg m0_10ub = component(retype(m0, BRW_REGISTER_TYPE_UB), 10);
+         fs_reg r0_11ub =
+            stride(suboffset(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UB), 11),
+                   0, 1, 0);
+         bld.exec_all().group(2, 0).MOV(m0_10ub, r0_11ub);
+      } else if (devinfo->ver >= 11) {
          chanbld.AND(m0_2, retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD),
                      brw_imm_ud(INTEL_MASK(30, 24)));