Mesa (main): aco: remove redundant s_and exec after nir_op_inot

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Module: Mesa
Branch: main
Commit: cd489e538878acff975a0e40dc92275d0e693a68
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=cd489e538878acff975a0e40dc92275d0e693a68

Author: Daniel Schürmann <daniel at schuermann.dev>
Date:   Wed Jun 23 17:11:09 2021 +0200

aco: remove redundant s_and exec after nir_op_inot

Totals from 22585 (15.04% of 150170) affected shaders: (GFX10.3)
VGPRs: 1474048 -> 1473904 (-0.01%)
CodeSize: 155238876 -> 155187688 (-0.03%); split: -0.06%, +0.03%
MaxWaves: 385086 -> 385122 (+0.01%)
Instrs: 29297735 -> 29284442 (-0.05%); split: -0.08%, +0.04%
Latency: 675841742 -> 675764151 (-0.01%); split: -0.02%, +0.01%
InvThroughput: 174859037 -> 174854796 (-0.00%); split: -0.01%, +0.01%
VClause: 479790 -> 479781 (-0.00%); split: -0.01%, +0.00%
SClause: 1106900 -> 1106615 (-0.03%); split: -0.03%, +0.01%
Copies: 1829037 -> 1828042 (-0.05%); split: -0.09%, +0.03%
Branches: 859971 -> 859967 (-0.00%); split: -0.00%, +0.00%
PreSGPRs: 1341850 -> 1342356 (+0.04%); split: -0.01%, +0.04%
PreVGPRs: 1327322 -> 1327034 (-0.02%)

Reviewed-by: Timur Kristóf <timur.kristof at gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11573>

---

 src/amd/compiler/aco_instruction_selection.cpp | 8 +-------
 1 file changed, 1 insertion(+), 7 deletions(-)

diff --git a/src/amd/compiler/aco_instruction_selection.cpp b/src/amd/compiler/aco_instruction_selection.cpp
index 1106b6f239b..ccad2f46904 100644
--- a/src/amd/compiler/aco_instruction_selection.cpp
+++ b/src/amd/compiler/aco_instruction_selection.cpp
@@ -1421,13 +1421,7 @@ visit_alu_instr(isel_context* ctx, nir_alu_instr* instr)
    }
    case nir_op_inot: {
       Temp src = get_alu_src(ctx, instr->src[0]);
-      if (instr->dest.dest.ssa.bit_size == 1) {
-         assert(src.regClass() == bld.lm);
-         assert(dst.regClass() == bld.lm);
-         /* Don't use s_andn2 here, this allows the optimizer to make a better decision */
-         Temp tmp = bld.sop1(Builder::s_not, bld.def(bld.lm), bld.def(s1, scc), src);
-         bld.sop2(Builder::s_and, Definition(dst), bld.def(s1, scc), tmp, Operand(exec, bld.lm));
-      } else if (dst.regClass() == v1 || dst.regClass() == v2b || dst.regClass() == v1b) {
+      if (dst.regClass() == v1 || dst.regClass() == v2b || dst.regClass() == v1b) {
          emit_vop1_instruction(ctx, instr, aco_opcode::v_not_b32, dst);
       } else if (dst.regClass() == v2) {
          Temp lo = bld.tmp(v1), hi = bld.tmp(v1);