Mesa (staging/21.2): pan/bi: Use CLPER_V6 on Mali G31

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Module: Mesa
Branch: staging/21.2
Commit: 2d587675f7f580fcab149e59e8516d28836c2de3
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=2d587675f7f580fcab149e59e8516d28836c2de3

Author: Alyssa Rosenzweig <alyssa at collabora.com>
Date:   Thu Aug 19 22:09:32 2021 +0000

pan/bi: Use CLPER_V6 on Mali G31

Apparently, CLPER_V7 is missing from Mali G31, but CLPER_V6 works. Fixes
INSTR_INVALID_ENC faults and failures in
dEQP-GLES3.functional.shaders.derivate.* on Dvalin.

Technically not an errata but an implementation difference. I suspect
Mali G51 will need this as well, should we ever allowlist it.

Signed-off-by: Alyssa Rosenzweig <alyssa at collabora.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12478>
(cherry picked from commit 61c8e39649cad466c7eccfb233d6be3327142452)

Conflicts:
	src/panfrost/bifrost/bi_quirks.h

---

 .pick_status.json                      |  2 +-
 src/panfrost/bifrost/bi_quirks.h       | 17 ++++++++++++++---
 src/panfrost/bifrost/bifrost_compile.c |  2 +-
 3 files changed, 16 insertions(+), 5 deletions(-)

diff --git a/.pick_status.json b/.pick_status.json
index 6d2b530792e..a65e308b7c1 100644
--- a/.pick_status.json
+++ b/.pick_status.json
@@ -733,7 +733,7 @@
         "description": "pan/bi: Use CLPER_V6 on Mali G31",
         "nominated": true,
         "nomination_type": 0,
-        "resolution": 0,
+        "resolution": 1,
         "main_sha": null,
         "because_sha": null
     },
diff --git a/src/panfrost/bifrost/bi_quirks.h b/src/panfrost/bifrost/bi_quirks.h
index ea674df9be1..481d3aa8fea 100644
--- a/src/panfrost/bifrost/bi_quirks.h
+++ b/src/panfrost/bifrost/bi_quirks.h
@@ -39,15 +39,26 @@
 
 #define BIFROST_NO_FP32_TRANSCENDENTALS (1 << 1)
 
+/* Whether this GPU lacks support for the full form of the CLPER instruction.
+ * These GPUs use a simple encoding of CLPER that does not support
+ * inactive_result, subgroup_size, or lane_op. Using those features requires
+ * lowering to additional ALU instructions. The encoding forces inactive_result
+ * = zero, subgroup_size = subgroup4, and lane_op = none. */
+
+#define BIFROST_LIMITED_CLPER (1 << 2)
+
 static inline unsigned
 bifrost_get_quirks(unsigned product_id)
 {
         switch (product_id >> 8) {
         case 0x60:
-                return BIFROST_NO_PRELOAD | BIFROST_NO_FP32_TRANSCENDENTALS;
+                return BIFROST_NO_PRELOAD | BIFROST_NO_FP32_TRANSCENDENTALS |
+                       BIFROST_LIMITED_CLPER;
         case 0x62:
-                return BIFROST_NO_PRELOAD;
-        case 0x70:
+                return BIFROST_NO_PRELOAD | BIFROST_LIMITED_CLPER;
+        case 0x70: /* G31 */
+                return BIFROST_LIMITED_CLPER;
+        case 0x71:
         case 0x72:
         case 0x74:
                 return 0;
diff --git a/src/panfrost/bifrost/bifrost_compile.c b/src/panfrost/bifrost/bifrost_compile.c
index 326dc0915d5..2fda3e85399 100644
--- a/src/panfrost/bifrost/bifrost_compile.c
+++ b/src/panfrost/bifrost/bifrost_compile.c
@@ -1971,7 +1971,7 @@ bi_emit_alu(bi_builder *b, nir_alu_instr *instr)
 
                 bi_index left, right;
 
-                if (b->shader->arch == 6) {
+                if (b->shader->quirks & BIFROST_LIMITED_CLPER) {
                         left = bi_clper_v6_i32(b, s0, lane1);
                         right = bi_clper_v6_i32(b, s0, lane2);
                 } else {