Mesa (main): 21 new commits

Wed Aug 25 23:17:39 UTC 2021

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=565f9105b70b2efd9cab34c218d90596a2d04ce0
Author: Nanley Chery <nanley.g.chery at intel.com>
Date:   Wed Jul 21 12:06:28 2021 -0700

    anv/image: Don't assert that HiZ can be added
    
    HiZ isn't yet enabled for Tile4/64.
    
    Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12132>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=0022a11ff4fbbe89c2511d758f807b286ebb1bd7
Author: Nanley Chery <nanley.g.chery at intel.com>
Date:   Tue Apr 6 11:45:22 2021 -0700

    iris: Disable tiled memcpy for Tile4
    
    ISL's tiled memcpy functions don't support it yet.
    
    Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12132>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=fd509ef59d7df598013330452600fdd838f56c19
Author: Jordan Justen <jordan.l.justen at intel.com>
Date:   Tue Jun 16 21:53:48 2020 -0700

    iris: Disable the Y-tiled modifiers on XeHP+
    
    I915_FORMAT_MOD_Y_TILED_CCS was already disabled for Xe+ due to a change
    in the CCS layout. Disable the remaining Y-tiled modifiers since XeHP
    lacks support for Y-tiling.
    
    Rework:
    * Nanley: Include Anuj's fix for the non-CCS modifiers.
    * Nanley: Split out Anuj's fix into a separate if statement.
    * Nanley: Rewrite commit message.
    
    Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
    Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12132>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=bd516c65814d5fdd70ce655b447c8a3ed7c98bb3
Author: Nanley Chery <nanley.g.chery at intel.com>
Date:   Fri Jul 23 16:37:47 2021 -0700

    intel/isl: Disable I915_FORMAT_MOD_Y_TILED on XeHP+
    
    XeHP lacks support for Y-tiling.
    
    Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12132>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=af40104e7da6aa37a801edc124a7709432d58289
Author: Nanley Chery <nanley.g.chery at intel.com>
Date:   Mon Jun 28 15:32:16 2021 -0700

    intel: Add underscores to HALIGN and VALIGN enums
    
    The HALIGN enums for XeHP already have underscores. Make the other
    HALIGN and VALIGN enums conform.
    
    Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12132>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=3d1f6342c0846e255d2dae04467797d816ff80a3
Author: Nanley Chery <nanley.g.chery at intel.com>
Date:   Mon Nov 12 13:59:06 2018 -0800

    intel: Update surface states for XeHP alignments
    
    Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12132>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=fbde743b0720d9f09778ca7bdb8a952d6978e986
Author: Nanley Chery <nanley.g.chery at intel.com>
Date:   Thu Jul 29 16:25:06 2021 -0700

    intel/isl: Use a switch for HALIGN/VALIGN encoding
    
    Avoid using a sparse and relatively large array for HALIGN encoding.
    Additionally, this provides validation of the input alignment values.
    
    Suggested-by: Jason Ekstrand <jason at jlekstrand.net>
    Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12132>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=2e464e69b956eab74a782ed7384cb609a937a50c
Author: Nanley Chery <nanley.g.chery at intel.com>
Date:   Fri Jul 30 10:50:59 2021 -0700

    intel/isl: Fix halign/valign of uncompressed views
    
    We're going to start asserting for valid halign/valign values during
    surface state emission. Pre-SKL, isl_surf_get_uncompressed_surf creates
    uncompressed surfaces with invalid halign/valign values - 1x1. Fix this
    by replacing the call to isl_surf_get_image_surf with isl_surf_init,
    passing in the uncompressed format up-front.
    
    As we're no longer using isl_surf_get_image_surf, we also need to get
    the x and y offset of the image ourselves. Instead of getting a
    sample-based offset, then converting to elements later on, we use
    isl_surf_get_image_offset_B_tile_el to get the offset in elements
    up-front.
    
    With the above two changes, the generic code after the else-block is no
    longer needed for the single-layer-view code path. We move it and
    specialize it to the if-block (which is executed SKL+ and handles
    multi-layer views).
    
    Cc: mesa-stable
    Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12132>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=c7bcbc950c04367c6abf54cb48ef930557dcea60
Author: Nanley Chery <nanley.g.chery at intel.com>
Date:   Fri Jul 30 14:31:05 2021 -0700

    intel/blorp: Fix Gfx7 stencil surface state valign
    
    Stencil on Gfx7 has a vertical alignment element of 8, but the largest
    its surface state can express is 4. Apply the Gfx6 solution of changing
    the alignment in blorp_surf_retile_w_to_y.
    
    Cc: mesa-stable
    Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12132>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=1f62cddaf537cd6fcfead26ac297a85727790ba0
Author: Nanley Chery <nanley.g.chery at intel.com>
Date:   Fri Jul 23 09:02:06 2021 -0700

    intel/blorp: Fix faked RGB image alignment on XeHP
    
    On XeHP, NPOT and POT formatted surfaces will use different image
    alignment units when emitting surface states. When BLORP fakes an RGB
    image as RED, update the image alignment to prevent assert failures when
    emitting surface states.
    
    Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12132>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=79ad9cda480ef810d93bfcc7912448a4503a457b
Author: Nanley Chery <nanley.g.chery at intel.com>
Date:   Mon Nov 12 13:59:06 2018 -0800

    intel: Support Tile4/64 in surface states
    
    Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12132>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=dd9ae2dc7be4289295f65f7f996b549016e4a984
Author: Nanley Chery <nanley.g.chery at intel.com>
Date:   Fri Nov 2 14:47:37 2018 -0700

    intel: Support Tile4/64 in depth/stencil state
    
    Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12132>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=f54de77c3a50070b1c7692a2319c7bafc8ea8358
Author: Nanley Chery <nanley.g.chery at intel.com>
Date:   Fri Nov 2 13:01:58 2018 -0700

    intel/isl: Update tiling filter functions for XeHP
    
    Enable the XeHP-specific tilings and restrict them to that platform.
    
    Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12132>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=0ab2fa18e4b2d1303f7043c6841aa93020512224
Author: Nanley Chery <nanley.g.chery at intel.com>
Date:   Thu Jul 29 17:04:14 2021 -0700

    intel/isl: Use an allow-list in gfx6_filter_tiling
    
    Try to avoid having to update isl_gfx6_filter_tiling when new tilings
    are added for new platforms. Note that the allow-list uses
    ISL_TILING_ANY_Y_MASK and thus assumes that no new Y-tilings will be
    added in the future.
    
    Suggested-by: Jason Ekstrand <jason at jlekstrand.net>
    Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12132>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=602f597bc10a6f01f588130c5f0d1d24d655a6c7
Author: Nanley Chery <nanley.g.chery at intel.com>
Date:   Thu Jul 29 17:16:44 2021 -0700

    intel/isl: Drop ISL_SURF_USAGE_DISPLAY_*_BIT
    
    We haven't used these since their introduction.
    
    Suggested-by: Jason Ekstrand <jason at jlekstrand.net>
    Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12132>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=ac37d7801c13a1630ec0c029e1792ace4891a571
Author: Nanley Chery <nanley.g.chery at intel.com>
Date:   Thu Jul 22 15:11:01 2021 -0700

    intel/isl: Drop extra assert on array_pitch_el_rows
    
    ISL already asserts that the variable is a multiple of the tile height
    via isl_assert_div.
    
    Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12132>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=4309012774872357cb791050db2a113723543fa9
Author: Nanley Chery <nanley.g.chery at intel.com>
Date:   Fri Nov 2 13:01:58 2018 -0700

    intel/isl: Size Tile64 surfaces with 4 dimensions
    
    In order to size Tile64 surfaces correctly, make sure that the total
    physical extent is arrayed. The code should handle 3D surfaces as well,
    but is untested for now.
    
    Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12132>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=8fd76782415b7498e4da29b477843cab1daeac76
Author: Nanley Chery <nanley.g.chery at intel.com>
Date:   Mon Nov 12 13:59:06 2018 -0800

    intel/isl: Update image alignments on XeHP
    
    Implement the new XeHP alignment rules for surface layout.
    RENDER_SURFACE_STATE objects still need updating, but that's left for a
    separate commit.
    
    Rework:
    * Nanley: Include Sagar's VALIGN fix for D16_UNORM.
    
    Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12132>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=0bcfa2d8fb8e29541089fb60a1f99d6fe09214d4
Author: Nanley Chery <nanley.g.chery at intel.com>
Date:   Fri Nov 2 13:01:58 2018 -0700

    intel/isl: Define ISL_TILING_4/64 for XeHP
    
    XeHP defines new tiling formats, Tile4 and Tile64. They are needed in
    order to support depth/stencil surfaces and multisampling. Create new
    ISL enums and define some initial tiling information in order to enable
    them later on.
    
    Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12132>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=44ef425ce88b90afcecf282a96201c630afebe74
Author: Nanley Chery <nanley.g.chery at intel.com>
Date:   Tue Mar 23 11:01:16 2021 -0700

    intel/isl: Add msaa_layout param to isl_tiling_get_info
    
    The additional parameter will be used by Tile64.
    
    Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12132>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=e307d46eabac25460709d4579ffc1c3be8a4ad56
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Wed Feb 21 14:57:46 2018 -0800

    intel/isl: Add more parameters to isl_tiling_get_info
    
    They are not used yet but the layout of Yf and Ys tiles are dependent on
    these parameters.  While we're here, better document the function.
    
    Rework:
    * Nanley: Update crocus.
    
    Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
    Reviewed-by: Nanley Chery <nanley.g.chery at intel.com>
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12132>