Mesa (staging/21.2): intel/blorp: Fix Gfx7 stencil surface state valign
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Fri Aug 27 17:23:31 UTC 2021
Module: Mesa
Branch: staging/21.2
Commit: ad37d530ce545f7f00393f9bc910defb817ccf92
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ad37d530ce545f7f00393f9bc910defb817ccf92
Author: Nanley Chery <nanley.g.chery at intel.com>
Date: Fri Jul 30 14:31:05 2021 -0700
intel/blorp: Fix Gfx7 stencil surface state valign
Stencil on Gfx7 has a vertical alignment element of 8, but the largest
its surface state can express is 4. Apply the Gfx6 solution of changing
the alignment in blorp_surf_retile_w_to_y.
Cc: mesa-stable
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12132>
(cherry picked from commit c7bcbc950c04367c6abf54cb48ef930557dcea60)
---
.pick_status.json | 2 +-
src/intel/blorp/blorp_blit.c | 4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/.pick_status.json b/.pick_status.json
index 9a8cae96778..8fe665a2b9e 100644
--- a/.pick_status.json
+++ b/.pick_status.json
@@ -949,7 +949,7 @@
"description": "intel/blorp: Fix Gfx7 stencil surface state valign",
"nominated": true,
"nomination_type": 0,
- "resolution": 0,
+ "resolution": 1,
"main_sha": null,
"because_sha": null
},
diff --git a/src/intel/blorp/blorp_blit.c b/src/intel/blorp/blorp_blit.c
index 17538e4f963..abd99ae271a 100644
--- a/src/intel/blorp/blorp_blit.c
+++ b/src/intel/blorp/blorp_blit.c
@@ -1649,8 +1649,8 @@ blorp_surf_retile_w_to_y(const struct isl_device *isl_dev,
blorp_surf_fake_interleaved_msaa(isl_dev, info);
}
- if (isl_dev->info->ver == 6) {
- /* Gfx6 stencil buffers have a very large alignment coming in from the
+ if (isl_dev->info->ver == 6 || isl_dev->info->ver == 7) {
+ /* Gfx6-7 stencil buffers have a very large alignment coming in from the
* miptree. It's out-of-bounds for what the surface state can handle.
* Since we have a single layer and level, it doesn't really matter as
* long as we don't pass a bogus value into isl_surf_fill_state().
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