Mesa (main): intel/compiler: Properly lower WorkgroupId for Task/Mesh
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Sat Dec 4 01:33:15 UTC 2021
Module: Mesa
Branch: main
Commit: 7938c38778c3a7bdf2471e5a7754a600849b5705
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=7938c38778c3a7bdf2471e5a7754a600849b5705
Author: Caio Oliveira <caio.oliveira at intel.com>
Date: Tue May 18 10:11:42 2021 -0700
intel/compiler: Properly lower WorkgroupId for Task/Mesh
Task/Mesh currently only support a single dimension (both in NV API
and HW), so make Y and Z be zero.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13661>
---
src/intel/compiler/brw_fs.cpp | 20 +++++++++++++-------
src/intel/compiler/brw_fs.h | 2 +-
src/intel/compiler/brw_fs_nir.cpp | 2 +-
3 files changed, 15 insertions(+), 9 deletions(-)
diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp
index 51db62f3e3f..8caae21d683 100644
--- a/src/intel/compiler/brw_fs.cpp
+++ b/src/intel/compiler/brw_fs.cpp
@@ -10082,19 +10082,25 @@ brw_compile_fs(const struct brw_compiler *compiler,
}
fs_reg *
-fs_visitor::emit_cs_work_group_id_setup()
+fs_visitor::emit_work_group_id_setup()
{
- assert(stage == MESA_SHADER_COMPUTE || stage == MESA_SHADER_KERNEL);
+ assert(gl_shader_stage_uses_workgroup(stage));
fs_reg *reg = new(this->mem_ctx) fs_reg(vgrf(glsl_type::uvec3_type));
struct brw_reg r0_1(retype(brw_vec1_grf(0, 1), BRW_REGISTER_TYPE_UD));
- struct brw_reg r0_6(retype(brw_vec1_grf(0, 6), BRW_REGISTER_TYPE_UD));
- struct brw_reg r0_7(retype(brw_vec1_grf(0, 7), BRW_REGISTER_TYPE_UD));
-
bld.MOV(*reg, r0_1);
- bld.MOV(offset(*reg, bld, 1), r0_6);
- bld.MOV(offset(*reg, bld, 2), r0_7);
+
+ if (gl_shader_stage_is_compute(stage)) {
+ struct brw_reg r0_6(retype(brw_vec1_grf(0, 6), BRW_REGISTER_TYPE_UD));
+ struct brw_reg r0_7(retype(brw_vec1_grf(0, 7), BRW_REGISTER_TYPE_UD));
+ bld.MOV(offset(*reg, bld, 1), r0_6);
+ bld.MOV(offset(*reg, bld, 2), r0_7);
+ } else {
+ /* Task/Mesh have a single Workgroup ID dimension in the HW. */
+ bld.MOV(offset(*reg, bld, 1), brw_imm_ud(0));
+ bld.MOV(offset(*reg, bld, 2), brw_imm_ud(0));
+ }
return reg;
}
diff --git a/src/intel/compiler/brw_fs.h b/src/intel/compiler/brw_fs.h
index a81a5f58b9a..8bc2dd29a4f 100644
--- a/src/intel/compiler/brw_fs.h
+++ b/src/intel/compiler/brw_fs.h
@@ -319,7 +319,7 @@ public:
unsigned base_offset, const nir_src &offset_src,
unsigned num_components, unsigned first_component);
void emit_cs_terminate();
- fs_reg *emit_cs_work_group_id_setup();
+ fs_reg *emit_work_group_id_setup();
void emit_barrier();
diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp
index dc13de3f058..2b2bccdf053 100644
--- a/src/intel/compiler/brw_fs_nir.cpp
+++ b/src/intel/compiler/brw_fs_nir.cpp
@@ -195,7 +195,7 @@ emit_system_values_block(nir_block *block, fs_visitor *v)
assert(gl_shader_stage_uses_workgroup(v->stage));
reg = &v->nir_system_values[SYSTEM_VALUE_WORKGROUP_ID];
if (reg->file == BAD_FILE)
- *reg = *v->emit_cs_work_group_id_setup();
+ *reg = *v->emit_work_group_id_setup();
break;
case nir_intrinsic_load_helper_invocation:
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