Mesa (main): intel/compiler: Don't store "scalar stage" bits on Gfx8 or Gfx9

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Module: Mesa
Branch: main
Commit: ff74d5dd1b83f090ece0a0594fe691eefe2875c0
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=ff74d5dd1b83f090ece0a0594fe691eefe2875c0

Author: Ian Romanick <ian.d.romanick at intel.com>
Date:   Fri Oct  8 12:09:04 2021 -0700

intel/compiler: Don't store "scalar stage" bits on Gfx8 or Gfx9

Since 1d71b1a311239, only Gfx7 and earlier have any vec4 stages ever.

Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14128>

---

 src/intel/compiler/brw_compiler.c | 7 +------
 1 file changed, 1 insertion(+), 6 deletions(-)

diff --git a/src/intel/compiler/brw_compiler.c b/src/intel/compiler/brw_compiler.c
index 6b94c66d686..24c911276df 100644
--- a/src/intel/compiler/brw_compiler.c
+++ b/src/intel/compiler/brw_compiler.c
@@ -206,12 +206,7 @@ brw_get_compiler_config_value(const struct brw_compiler *compiler)
 {
    uint64_t config = 0;
    insert_u64_bit(&config, compiler->precise_trig);
-   if (compiler->devinfo->ver >= 8 && compiler->devinfo->ver < 10) {
-      insert_u64_bit(&config, compiler->scalar_stage[MESA_SHADER_VERTEX]);
-      insert_u64_bit(&config, compiler->scalar_stage[MESA_SHADER_TESS_CTRL]);
-      insert_u64_bit(&config, compiler->scalar_stage[MESA_SHADER_TESS_EVAL]);
-      insert_u64_bit(&config, compiler->scalar_stage[MESA_SHADER_GEOMETRY]);
-   }
+
    uint64_t mask = DEBUG_DISK_CACHE_MASK;
    while (mask != 0) {
       const uint64_t bit = 1ULL << (ffsll(mask) - 1);